Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=linux-4.13.y 2017-06-15T23:56:53+00:00 2017-06-15T23:56:53+00:00 Dave Airlie airlied@redhat.com 2017-06-15T23:54:02+00:00 urn:sha1:04d4fb5fa63876d8e7cf67f2788aecfafc6a28a7 New radeon and amdgpu features for 4.13: - Lots of Vega10 bug fixes - Preliminary Raven support - KIQ support for compute rings - MEC queue management rework from Andres - Audio support for DCE6 - SR-IOV improvements - Improved module parameters for controlling radeon vs amdgpu support for SI and CIK - Bug fixes - General code cleanups [airlied: dropped drmP.h header from one file was needed and build broke] * 'drm-next-4.13' of git://people.freedesktop.org/~agd5f/linux: (362 commits) drm/amdgpu: Fix compiler warnings drm/amdgpu: vm_update_ptes remove code duplication drm/amd/amdgpu: Port VCN over to new SOC15 macros drm/amd/amdgpu: Port PSP v10.0 over to new SOC15 macros drm/amd/amdgpu: Port PSP v3.1 over to new SOC15 macros drm/amd/amdgpu: Port NBIO v7.0 driver over to new SOC15 macros drm/amd/amdgpu: Port NBIO v6.1 driver over to new SOC15 macros drm/amd/amdgpu: Port UVD 7.0 over to new SOC15 macros drm/amd/amdgpu: Port MMHUB over to new SOC15 macros drm/amd/amdgpu: Cleanup gfxhub read-modify-write patterns drm/amd/amdgpu: Port GFXHUB over to new SOC15 macros drm/amd/amdgpu: Add offset variant to SOC15 macros drm/amd/powerplay: add avfs control for Vega10 drm/amdgpu: add virtual display support for raven drm/amdgpu/gfx9: fix compute ring doorbell index drm/amd/amdgpu: Rename KIQ ring to avoid spaces drm/amd/amdgpu: gfx9 tidy ups (v2) drm/amdgpu: add contiguous flag in ucode bo create drm/amdgpu: fix missed gpu info firmware when cache firmware during S3 drm/amdgpu: export test ib debugfs interface ... 2017-06-06T20:59:30+00:00 Huang Rui ray.huang@amd.com 2017-05-31T02:35:42+00:00 urn:sha1:916910ad916a5c63dcd724a557bab092abdb9e7b Something writes over the first 8 MB so reserve this on vega10 until we root cause it. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2017-05-24T22:23:55+00:00 Tom St Denis tom.stdenis@amd.com 2017-05-23T15:35:22+00:00 urn:sha1:9156e723301c0a7a7def4cde820e018ce791b842 If you initiate a read that is out of the VRAM address space return ENXIO instead of 0. Reads that begin below that point will read upto the VRAM limit as before. Cc: stable@vger.kernel.org Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2017-05-24T21:40:31+00:00 Roger.He Hongbo.He@amd.com 2017-05-05T05:27:10+00:00 urn:sha1:738f64ccc237f80b7673a6cc43051916eb90dc27 to cover below case: 1. A task gart bind/unbind but not add to adev->gtt_list yet 2. at this time gpu reset, gtt only recover those gtt in adev->gtt_list Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Roger.He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2017-05-18T13:24:30+00:00 Sean Paul seanpaul@chromium.org 2017-05-18T13:24:30+00:00 urn:sha1:6b7781b42dc9bc9bcd1523b6c24b876cdda0bef3 Picking up drm-next @ 4.12-rc1 in order to apply Michal Hocko's vmalloc patch set Signed-off-by: Sean Paul <seanpaul@chromium.org> 2017-05-16T15:17:41+00:00 Masahiro Yamada yamada.masahiro@socionext.com 2017-04-24T04:50:21+00:00 urn:sha1:248a1d6f1ac410d3ed3907c1be2502e286f59bb8 Include <drm/*.h> instead of relative path from include/drm, then remove the -Iinclude/drm compiler flag. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1493009447-31524-4-git-send-email-yamada.masahiro@socionext.com 2017-05-05T22:12:28+00:00 Monk Liu Monk.Liu@amd.com 2017-04-27T09:14:57+00:00 urn:sha1:1d1a2cd58f05da1167c04394292aef9fbcf29bff otherwise we'll lost the high 32 bit for pte, which lead to incorrect MTYPE for vega10. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2017-04-28T21:33:16+00:00 Michel Dänzer michel.daenzer@amd.com 2017-04-28T08:28:14+00:00 urn:sha1:c81a1a74037f61c578f6b8218b079aa434e300b4 Some of these paths probably cannot be interrupted by a signal anyway. Those that can would fail to clean up things if they actually got interrupted. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2017-04-28T21:32:53+00:00 Chunming Zhou David1.Zhou@amd.com 2017-04-13T08:16:51+00:00 urn:sha1:05a72a2864c2b27471e9f5365448563c78f9b114 Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2017-04-28T21:32:52+00:00 Christian König christian.koenig@amd.com 2017-04-20T10:11:47+00:00 urn:sha1:4fcae787866915161f22d627328fa8d2e13d215b BOs not mapped into the GART are always valuable for an eviction. Otherwise we don't correctly swap them out on VRAM evictions during memory pressure. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>