kernel/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h, branch v6.1.168Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v6.1.1682022-09-30T20:59:00+00:00drm/amdgpu: add helper to init rlc firmware2022-09-30T20:59:00+00:00Hawking ZhangHawking.Zhang@amd.com2022-09-15T16:21:50+00:00urn:sha1:04fa38cce6e02be4362cd889780d58ec275c4d26
To initialzie rlc firmware according to rlc
firmware header version
v2: squash in backwards compat fix
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: add TAP_DELAYS upload support for gfx102022-07-25T13:31:04+00:00Chengming GuiJack.Gui@amd.com2022-07-15T05:12:14+00:00urn:sha1:2207efdd8388bd300a0051b1775705d890abd306
Support {GLOBAL/SE0/SE1/SE2/SE3}_TAP_DELAYS uploading.
v2: upload TAP_DELAYS before RLC autoload was triggered. (Hawking)
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add rlc TOC header file for soc21 (v2)2022-05-04T14:03:04+00:00Likun GaoLikun.Gao@amd.com2021-06-27T14:33:29+00:00urn:sha1:89466f49b285fe162dad5a22471673a3463145c9
Add RLC autoload TOC header file for soc21 ASIC.
v2: squash in updates
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: support rlc v2_3 ucode struct2022-05-04T14:02:38+00:00Likun GaoLikun.Gao@amd.com2021-08-30T03:07:59+00:00urn:sha1:550bb28e64a0200dbc04476fac880f86f914ad36
Add support for rlc v2_3 to support RLCV and RLCP fw load.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: retire rlc callbacks sriov_rreg/wreg2022-01-25T23:00:33+00:00Hawking ZhangHawking.Zhang@amd.com2022-01-17T06:33:23+00:00urn:sha1:381519dff88845bbe522e7446ec1e32e351c670d
Not needed anymore.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Zhou, Peng Ju <PengJu.Zhou@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add structures for rlcg indirect reg access2022-01-25T23:00:33+00:00Hawking ZhangHawking.Zhang@amd.com2022-01-18T08:11:02+00:00urn:sha1:b12252b0538183d8b88bd4a8d8d05a808c46472c
Add structures that are used to cache registers offsets
for rlcg indirect reg access ctrl and flag availability
of such interface
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Zhou, Peng Ju <PengJu.Zhou@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Change the imprecise function name2021-07-23T14:07:59+00:00Roy SunRoy.Sun@amd.com2021-07-05T09:47:57+00:00urn:sha1:1a4772d922d2f3a46903ca699f7e0a3fa3bb448c
The callback functions are used for SRIOV read/write instead
of just for rlcg read/write
Signed-off-by: Roy Sun <Roy.Sun@amd.com>
Reviewed-by: Zhou pengju <pengju.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Indirect register access for Navi12 sriov2021-05-21T14:32:06+00:00Peng Ju ZhouPengJu.Zhou@amd.com2021-05-14T06:26:46+00:00urn:sha1:a5504e9ad48ac523afffba417e5a77d5c09af003
This patch series are used for GC/MMHUB(part)/IH_RB_CNTL
indirect access in the SRIOV environment.
There are 4 bits, controlled by host, to control
if GC/MMHUB(part)/IH_RB_CNTL indirect access enabled.
(one bit is master bit controls other 3 bits)
For GC registers, changing all the register access from MMIO to
RLC and use RLC as the default access method in the full access time.
For partial MMHUB registers, changing their access from MMIO to
RLC in the full access time, the remaining registers
keep the original access method.
For IH_RB_CNTL register, changing it's access from MMIO to PSP.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: indirect register access for nv12 sriov2021-04-09T20:50:17+00:00Peng Ju ZhouPengJu.Zhou@amd.com2021-03-22T07:18:01+00:00urn:sha1:5e025531b773ee9789a9a9948fc7e74e6077ddd5
1. expand rlcg interface for gc & mmhub indirect access
2. add rlcg interface for no kiq
v2: squash in fix for gfx9 (Changfeng)
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
Reviewed-by: Emily.Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add rlc iram and dram firmware support2020-10-21T21:33:42+00:00Likun GaoLikun.Gao@amd.com2020-09-30T06:34:08+00:00urn:sha1:843c7eb2f7571aa092a8ea010c80e8d94c197f67
Support to load RLC iram and dram ucode when RLC firmware struct use v2.2
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>