<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h, branch v6.6.142</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.142</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.142'/>
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<updated>2026-05-17T15:13:46+00:00</updated>
<entry>
<title>drm/amdgpu: Add bounds checking to ib_{get,set}_value</title>
<updated>2026-05-17T15:13:46+00:00</updated>
<author>
<name>Benjamin Cheng</name>
<email>benjamin.cheng@amd.com</email>
</author>
<published>2026-03-25T12:39:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=0fb5cb556b249b2b64c0f818136c4c3e838ef53f'/>
<id>urn:sha1:0fb5cb556b249b2b64c0f818136c4c3e838ef53f</id>
<content type='text'>
commit 66085e206431ef88ce36f53c1f53d570790ccc9e upstream.

The uvd/vce/vcn code accesses the IB at predefined offsets without
checking that the IB is large enough. Check the bounds here. The caller
is responsible for making sure it can handle arbitrary return values.

Also make the idx a uint32_t to prevent overflows causing the condition
to fail.

Signed-off-by: Benjamin Cheng &lt;benjamin.cheng@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Ruijing Dong &lt;ruijing.dong@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: switch job hw_fence to amdgpu_fence</title>
<updated>2025-07-06T09:00:15+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-06-02T15:31:52+00:00</published>
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<id>urn:sha1:8302adf60aba60da707af566801c0641c8d367c9</id>
<content type='text'>
commit ebe43542702c3d15d1a1d95e8e13b1b54076f05a upstream.

Use the amdgpu fence container so we can store additional
data in the fence.  This also fixes the start_time handling
for MCBP since we were casting the fence to an amdgpu_fence
and it wasn't.

Fixes: 3f4c175d62d8 ("drm/amdgpu: MCBP based on DRM scheduler (v9)")
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit bf1cd14f9e2e1fdf981eed273ddd595863f5288c)
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Clean up errors in amdgpu_ring.h</title>
<updated>2023-08-09T13:43:45+00:00</updated>
<author>
<name>Ran Sun</name>
<email>sunran001@208suo.com</email>
</author>
<published>2023-08-02T07:28:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=1b01c010d7e830db8cec9dee7bb919c9fded43a2'/>
<id>urn:sha1:1b01c010d7e830db8cec9dee7bb919c9fded43a2</id>
<content type='text'>
Fix the following errors reported by checkpatch:

ERROR: spaces required around that ':' (ctx:VxW)

Signed-off-by: Ran Sun &lt;sunran001@208suo.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add amdgpu_error_* debugfs file</title>
<updated>2023-06-15T15:37:54+00:00</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2023-04-19T10:51:41+00:00</published>
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<id>urn:sha1:b13eb02ba8ba7617d41212121891756da31f1d8b</id>
<content type='text'>
This allows us to insert some error codes into the bottom of the pipeline
on an engine.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Modify indirect buffer packages for resubmission</title>
<updated>2023-06-09T16:44:15+00:00</updated>
<author>
<name>Jiadong Zhu</name>
<email>Jiadong.Zhu@amd.com</email>
</author>
<published>2023-05-25T08:52:55+00:00</published>
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<id>urn:sha1:8ff865be93e642d0ad66ca7369f42fbe36dc6a90</id>
<content type='text'>
When the preempted IB frame resubmitted to cp, we need to modify the frame
data including:
1. set PRE_RESUME 1 in CONTEXT_CONTROL.
2. use meta data(DE and CE) read from CSA in WRITE_DATA.

Add functions to save the location the first time IBs emitted and callback
to patch the package when resubmission happens.

Signed-off-by: Jiadong Zhu &lt;Jiadong.Zhu@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add partition ID track in ring</title>
<updated>2023-06-09T13:59:30+00:00</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2022-08-15T20:45:12+00:00</published>
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<id>urn:sha1:797a0a142ca7f3b823ae1032983111c055bc50fb</id>
<content type='text'>
Keep track partition ID in ring.

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Acked-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: increase AMDGPU_MAX_RINGS</title>
<updated>2023-06-09T13:54:05+00:00</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2023-03-16T03:08:06+00:00</published>
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<id>urn:sha1:bb0ed57b4450e46de3651b310dcb4273032c3122</id>
<content type='text'>
On newer GPUs, the number of kernel rings are increased.

Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: increase AMDGPU_MAX_HWIP_RINGS</title>
<updated>2023-06-09T13:51:51+00:00</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2023-01-10T14:01:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=1bd99ca2695a76f15d7f7862d6ef878588e854dc'/>
<id>urn:sha1:1bd99ca2695a76f15d7f7862d6ef878588e854dc</id>
<content type='text'>
[WA] Increase AMDGPU_MAX_HWIP_RINGS to 64 to support more compute
ring resource. Later need redesign with queue/prirority/scheduler
factors to reduce AMDGPU_MAX_HWIP_RINGS.

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: increase MAX setting to hold more jpeg instances</title>
<updated>2023-06-09T13:51:19+00:00</updated>
<author>
<name>James Zhu</name>
<email>James.Zhu@amd.com</email>
</author>
<published>2022-12-12T17:29:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=45ed97ad36b744dfc2754c47cfd4423aab6322a2'/>
<id>urn:sha1:45ed97ad36b744dfc2754c47cfd4423aab6322a2</id>
<content type='text'>
vcn_v4_0_3 increased jpeg instances,
need increasing MAX resources setting accordlingly.

Signed-off-by: James Zhu &lt;James.Zhu@amd.com&gt;
Acked-by Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: adjust some basic elements for multiple AID case</title>
<updated>2023-06-09T13:43:35+00:00</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2022-02-23T03:43:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=386ea27c3b0bcdd5b5be74bdf26022ab931eae7b'/>
<id>urn:sha1:386ea27c3b0bcdd5b5be74bdf26022ab931eae7b</id>
<content type='text'>
add some elements below:
 - num_aid
 - aid_id for each sdma instance
 - num_inst_per_aid for sdma

and extend macro size below:
 - SDMA_MAX_INSTANCES to 16
 - AMDGPU_MAX_RINGS to 96
 - AMDGPU_MAX_HWIP_RINGS to 32

v2: move aid_id from amdgpu_ring to amdgpu_sdma_instance. (Lijo)

Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Acked-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
