kernel/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c, branch linux-4.13.y

drm/amdgpu: Move compute vm bug logic to amdgpu_vm.c

2017-06-01T20:00:20+00:00

In review, Christian would like to keep the logic inside amdgpu_vm.c with a cost of slightly slower. The loop is still optimized out with this patch. v2: remove the if statement. Now it is not slower. Signed-off-by: Alex Xie Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: guarantee bijective mapping of ring ids for LRU v3

2017-05-31T20:49:03+00:00

Depending on usage patterns, the current LRU policy may create a non-injective mapping between userspace ring ids and kernel rings. This behaviour is undesired as apps that attempt to fill all HW blocks would be unable to reach some of them. This change forces the LRU policy to create bijective mappings only. v2: compress ring_blacklist v3: simplify amdgpu_ring_is_blacklisted() logic Signed-off-by: Andres Rodriguez Reviewed-by: Nicolai Hähnle Signed-off-by: Alex Deucher

drm/amdgpu: implement lru amdgpu_queue_mgr policy for compute v4

2017-05-31T20:49:02+00:00

Use an LRU policy to map usermode rings to HW compute queues. Most compute clients use one queue, and usually the first queue available. This results in poor pipe/queue work distribution when multiple compute apps are running. In most cases pipe 0 queue 0 is the only queue that gets used. In order to better distribute work across multiple HW queues, we adopt a policy to map the usermode ring ids to the LRU HW queue. This fixes a large majority of multi-app compute workloads sharing the same HW queue, even though 7 other queues are available. v2: use ring->funcs->type instead of ring->hw_ip v3: remove amdgpu_queue_mapper_funcs v4: change ring_lru_list_lock to spinlock, grab only once in lru_get() Signed-off-by: Andres Rodriguez Signed-off-by: Alex Deucher

drm/amdgpu: Optimize a function called by every IB sheduling

2017-05-31T18:16:38+00:00

Move several if statements and a loop statment from run time to initialization time. Signed-off-by: Alex Xie Reviewed-by: Chunming Zhou Signed-off-by: Alex Deucher

drm/amd/amdgpu: Correct ring wptr address in debugfs (v2)

2017-03-30T03:55:53+00:00

On gfx9 hardware the value is not wrapped and is a 64-bit value. So we reduce it modulo the ring size. Signed-off-by: Tom St Denis Reviewed-by: Christian König (v2) use buf_mask instead of computing on the fly Signed-off-by: Alex Deucher

drm/amdgpu:fix ring init sequence

2017-03-30T03:55:38+00:00

ring->buf_mask need be set prior to ring_clear_ring invoke and fix ring_clear_ring as well which should use buf_mask instead of ptr_mask Signed-off-by: Monk Liu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: add 64bit wb functions

2017-03-30T03:53:35+00:00

Newer asics need 64 bit writeback slots. Reviewed-by: Christian König Signed-off-by: Ken Wang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: change wptr to 64 bits (v2)

2017-03-30T03:53:35+00:00

Newer asics need 64 bit wptrs. If the wptr is now smaller than the rptr that doesn't indicate a wrap-around anymore. v2: integrate Christian's comments. Signed-off-by: Ken Wang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu:use clear_ring to clr RB

2017-03-30T03:53:14+00:00

In resume routine, we need clr RB prior to the ring test of engine, otherwise some engine hang duplicated during GPU reset. Signed-off-by: Monk Liu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu:set cond_exec polling value to 1 in ring_init

2017-01-27T16:13:37+00:00

no need to set it per ib_schedule(), hw won't override this polling address. Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher