<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c, branch v5.4.130</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v5.4.130</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v5.4.130'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2020-01-17T18:48:51+00:00</updated>
<entry>
<title>drm/amdgpu: cleanup creating BOs at fixed location (v2)</title>
<updated>2020-01-17T18:48:51+00:00</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2019-09-13T11:43:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=1601575529051ee903105054683d202929e07ad5'/>
<id>urn:sha1:1601575529051ee903105054683d202929e07ad5</id>
<content type='text'>
commit de7b45babd9be25138ff5e4a0c34eefffbb226ff upstream.

The placement is something TTM/BO internal and the RAS code should
avoid touching that directly.

Add a helper to create a BO at a fixed location and use that instead.

v2: squash in fixes (Alex)

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>drm/amdgpu: correct ras error count type</title>
<updated>2019-08-23T16:30:32+00:00</updated>
<author>
<name>Guchun Chen</name>
<email>guchun.chen@amd.com</email>
</author>
<published>2019-08-16T07:06:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=64cc5414fbf673cf676e257f9d6c999357947488'/>
<id>urn:sha1:64cc5414fbf673cf676e257f9d6c999357947488</id>
<content type='text'>
Use unsigned long type for the same ras count variable.
This will avoid overflow on 64 bit system.

Signed-off-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Reviewed-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: remove ras block's feature status info in sysfs</title>
<updated>2019-08-12T17:47:48+00:00</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2019-08-09T09:39:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=5212a3bdf03f24a5ed3eabf8fc4833aa3c5287a3'/>
<id>urn:sha1:5212a3bdf03f24a5ed3eabf8fc4833aa3c5287a3</id>
<content type='text'>
feature mask info is enough for rocm tool,
"cat /sys/class/drm/card0/device/ras/features" will get the
info like this:

feature mask: 0x3ffb

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: support mmhub ras in amdgpu ras</title>
<updated>2019-08-12T17:47:48+00:00</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2019-08-06T12:22:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9fb2d8de4a43e7d92d1d53c0d4ebdda0a0ddc8d7'/>
<id>urn:sha1:9fb2d8de4a43e7d92d1d53c0d4ebdda0a0ddc8d7</id>
<content type='text'>
call mmhub ras query/inject in amdgpu ras

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add sub block parameter in ras inject command</title>
<updated>2019-08-12T17:47:48+00:00</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2019-08-07T06:27:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=44494f96ba962c6e0a0d8b1c0db5e7b54c75ab3a'/>
<id>urn:sha1:44494f96ba962c6e0a0d8b1c0db5e7b54c75ab3a</id>
<content type='text'>
ras sub block index could be passed from shell command

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Reviewed-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: update ras sysfs feature info</title>
<updated>2019-08-06T18:52:52+00:00</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2019-08-05T07:48:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=2a3c7ff6e37c0d0bf8d8e9031922d41c2409d7e5'/>
<id>urn:sha1:2a3c7ff6e37c0d0bf8d8e9031922d41c2409d7e5</id>
<content type='text'>
remove confused ras error type info

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: replace AMDGPU_RAS_UE with AMDGPU_RAS_SUCCESS</title>
<updated>2019-08-02T15:30:39+00:00</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2019-08-01T09:30:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=bd2280da46dbdbc3d70dc538f0613afb6fcc4efa'/>
<id>urn:sha1:bd2280da46dbdbc3d70dc538f0613afb6fcc4efa</id>
<content type='text'>
ce can also trigger interrupt, and even both ce and ue error can be
found in one ras query, distinguishing between ce and ue in interrupt
handler is uncessary.

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Suggested-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: support ce interrupt in ras module</title>
<updated>2019-08-02T15:30:38+00:00</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2019-07-29T08:04:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=51437623a0a14a5af74aee144a0f2d5790ab1420'/>
<id>urn:sha1:51437623a0a14a5af74aee144a0f2d5790ab1420</id>
<content type='text'>
correctable error can also trigger interrupt in some ras blocks

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add error address query for umc ras</title>
<updated>2019-08-02T15:30:38+00:00</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2019-08-01T03:41:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=13b7c46c18e26182450d01efd0988e5c9fa8260f'/>
<id>urn:sha1:13b7c46c18e26182450d01efd0988e5c9fa8260f</id>
<content type='text'>
umc error address query can get ce/ue error address and clear error
status

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: support gfx ras error injection and err_cnt query</title>
<updated>2019-07-31T19:51:14+00:00</updated>
<author>
<name>Dennis Li</name>
<email>Dennis.Li@amd.com</email>
</author>
<published>2019-07-31T12:45:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=83b0582c90576dd838bfbec84579f7e674cf59b2'/>
<id>urn:sha1:83b0582c90576dd838bfbec84579f7e674cf59b2</id>
<content type='text'>
check gfx error count in both ras querry function and
ras interrupt handler.

gfx ras is still disabled by default due to known stability
issue found in gpu reset.

Signed-off-by: Dennis Li &lt;Dennis.Li@amd.com&gt;
Reviewed-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
