kernel/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h, branch v6.6.134Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.1342023-08-09T13:46:05+00:00drm/amdgpu: Add pcie usage callback to nbio2023-08-09T13:46:05+00:00Asad Kamalasad.kamal@amd.com2023-07-28T09:58:54+00:00urn:sha1:8d759dc6644df4141a151293cb0e77fd8ca379ed
Add a callback in nbio to get pcie usage
Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Shiwu Zhang <shiwu.zhang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add pcie replay count callback to nbio2023-08-07T21:14:06+00:00Lijo Lazarlijo.lazar@amd.com2023-07-27T09:15:49+00:00urn:sha1:900af4e4887ca980c8d57889e3d33e36b7586f38
Add a callback in nbio to get pcie replay count.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Remove unused NBIO interface2023-06-15T18:33:56+00:00Lijo Lazarlijo.lazar@amd.com2023-06-13T10:48:46+00:00urn:sha1:0e41639d9a46b0285cd6381482037095f196d516
Set compute partition mode interface in NBIO is no longer used. Remove
the only implementation from NBIO v7.9
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Get supported memory partition modes2023-06-09T13:56:54+00:00Lijo Lazarlijo.lazar@amd.com2023-02-17T04:02:44+00:00urn:sha1:0f2e1d620eca56c4ceebc041aabb1eda26b2cfd0
Expand the interface to get supported memory partition modes also along
with the current memory partition mode.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add initial version of XCP routines2023-06-09T13:49:31+00:00Lijo Lazarlijo.lazar@amd.com2022-09-16T07:13:35+00:00urn:sha1:75d1692393cb78b510ff18733457f91d002452f7
Within a device, an accelerator core partition can be constituted with
different IP instances. These partitions are spatial in nature. Number
of partitions which can exist at the same time depends on the 'partition
mode'. Add a manager entity which is responsible for switching between
different partition modes and maintaining partitions. It is also
responsible for suspend/resume of different partitions.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: detect current GPU memory partition mode2023-06-09T13:48:42+00:00Rajneesh Bhardwajrajneesh.bhardwaj@amd.com2022-04-05T17:00:13+00:00urn:sha1:ea2d2f8ececdd4c778b66e19b82ce278dfc5e1c4
- Add helpers to detect the current GPU memory partition.
- Add current memory partition mode sysfs node.
Tested-by: Ori Messinger <Ori.Messinger@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add indirect r/w interface for smn address greater than 32bits2023-06-09T13:45:29+00:00Le Male.ma@amd.com2022-04-02T11:39:59+00:00urn:sha1:0c552ed38780f24b7ac235c3d10c6c94686ecfdf
On multiple AIDs platform, bit[34:32] in SMD address is leveraged to access
nonAID0 register smn address and new PCI_INDEX_HI register is introduced
to access the higher bits.
v2: rebase on latest register accessors (Alex)
Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add sysfs node for compute partition mode2023-06-09T13:40:25+00:00Le Male.ma@amd.com2022-05-17T14:20:10+00:00urn:sha1:98a54e88e87f7291d4bbc6ec646c498f64ae042f
Add current/available compute partitin mode sysfs node.
v2: make the sysfs node as IP independent one in amdgpu_gfx.c
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Rework pcie_bif ras sw_init2023-03-15T22:45:27+00:00Hawking ZhangHawking.Zhang@amd.com2023-03-13T06:18:34+00:00urn:sha1:fdc94d3a8c887e4e06a7ff8dcb51d55cd70e16cf
pcie_bif ras blocks needs to be initialized as early
as possible to handle fatal error detected in hw_init
phase. also align the pcie_bif ras sw_init with other
ras blocks
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Stanley Yang <Stanley.Yang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add nbio v4_3_0 ip block v22022-05-04T13:52:44+00:00Stanley.YangStanley.Yang@amd.com2022-04-04T21:28:13+00:00urn:sha1:0d09a60e3ebddb4c1bf595cef89d796a0afe96ac
This adds nbio v4_3_0 ip block support
Changed from v1:
use WREG32_SOC15/RREG32_SOC15 instead of
WREG32_PCIE/RREG32_PCIE
remove the programming of PCIE_CONFIG_CNTL
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>