Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v7.0-rc7 2026-01-27T23:02:06+00:00 2026-01-27T23:02:06+00:00 Tvrtko Ursulin tvrtko.ursulin@igalia.com 2026-01-12T10:22:33+00:00 urn:sha1:f7e06786512e730f750138b1221b6342bcf07859 Commit cb17fff3a254 ("drm/amdgpu/mes: remove unused functions") removed most of the code using these IDRs but forgot to remove the struct members and init/destroy paths. There is also interrupt handling code in SDMA 5.0 and 5.2 which appears to be using it, but is is unreachable since nothing ever allocates the relevant IDR. We replace those with one time warnings just to avoid any functional difference, but it is also possible they should be removed. v2: also fix up gfx_v12_1.c and sdma_v7_1.c Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> References: cb17fff3a254 ("drm/amdgpu/mes: remove unused functions") Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2025-12-10T22:39:09+00:00 Mukul Joshi mukul.joshi@amd.com 2025-04-29T02:08:10+00:00 urn:sha1:3235a5b72317be613b69e22c3b2c9f2bec546253 Currently, we do not turn off retry faults in VM_CONTEXT_CNTL value when passing it to MES if XNACK is off. This creates a situation where XNACK is disabled in SQ but enabled in UTCL2, which is not recommended. As a result, turn off/on retry faults in both SQ and UTCL2 when passing vm_context_cntl value to MES if XNACK is disabled/enabled. Suggested-by: Jay Cornwall <jay.cornwall@amd.com> Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2025-12-10T22:39:06+00:00 Mukul Joshi mukul.joshi@amd.com 2025-03-27T02:16:21+00:00 urn:sha1:cc52af1a961ff85ee1940d8d843dfc8f374f81b5 GFX 12.1.0 will support enabling/disabling XNACK on a per- process basis. This change enables the per process XNACK feature. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2025-12-08T19:13:15+00:00 Jack Xiao Jack.Xiao@amd.com 2025-03-10T09:02:36+00:00 urn:sha1:75053887d6d8f527578ffcb1113bc336fae49b42 Add initial cooperative dispatch MES support. a. set shared cmd buffer for the group of cooperative dispatch mes. b. automatically dispatch add_hw_queue/remove_hw_queue to master mes. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2025-12-08T18:56:29+00:00 Jack Xiao Jack.Xiao@amd.com 2024-11-21T08:22:38+00:00 urn:sha1:d09c7e266c8cd5590db59693ea3c3a66a55e63ab a. extend mes pipe instances to num_xcc * max_mes_pipe b. initialize mes schq/kiq pipes per xcc c. submit mes packet to mes ring according to xcc_id v2: rebase (Alex) Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2025-10-20T22:25:41+00:00 Victor Zhao Victor.Zhao@amd.com 2025-10-09T02:42:48+00:00 urn:sha1:6169b555db1392e79159e114fff105987231e4ce Currently SRIOV runtime will use kiq to write HDP_MEM_FLUSH_CNTL for hdp flush. This register need to be write from CPU for nbif to aware, otherwise it will not work. Implement amdgpu_kiq_hdp_flush and use kiq to do gpu hdp flush during sriov runtime. v2: - fallback to amdgpu_asic_flush_hdp when amdgpu_kiq_hdp_flush failed - add function amdgpu_mes_hdp_flush v3: - changed returned error Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2025-10-13T18:14:36+00:00 Jonathan Kim jonathan.kim@amd.com 2025-06-18T14:45:55+00:00 urn:sha1:72ea12f6be3bb57c2118189f7a7cfeb1f7c2748c Remove queue after reset flag is required to remove a queue that has been successfully reset to clean up the MES' internal state. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2025-10-13T18:14:28+00:00 Jonathan Kim jonathan.kim@amd.com 2025-10-09T15:28:19+00:00 urn:sha1:0ef930e1faca6418316e5b9a3b4d1f6ae9e5b240 By design the MES will return an array result that is twice the number of hung doorbells it can report. i.e. if up k reported doorbells are supported, then the second half of the array, also of length k, holds the HQD information (type/queue/pipe) where queue 1 corresponds to index 0 and k, queue 2 corresponds to index 1 and k + 1 etc ... The driver will use the HDQ info to target queue/pipe reset for hardware scheduled user compute queues. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2025-09-05T21:38:31+00:00 Jesse.Zhang Jesse.Zhang@amd.com 2025-09-04T01:39:34+00:00 urn:sha1:78e1222fbf0026de99420bc35c6c12931e0f36ee Helper function to detect and reset hung queues. MES will return an array of doorbell indices of which queues are hung and were optionally reset. v2: Clear the doorbell array before detection Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2025-08-27T17:57:51+00:00 Shaoyun Liu shaoyun.liu@amd.com 2025-07-11T01:42:16+00:00 urn:sha1:87e65052616c53676a4f9ae3def290fc489215e2 From MES version 0x81, it provide the new API INV_TLBS that support invalidate tlbs with PASID. Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>