Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v7.2-rc1 2026-06-04T19:25:46+00:00 2026-06-04T19:25:46+00:00 Sunil Khatri sunil.khatri@amd.com 2026-06-01T14:41:17+00:00 urn:sha1:dd7bd8e0f0c47361a3a513d6aa8ea2b36dd70deb MES firmware should report the same version whether read from the register or from the firmware ucode binary. This is not always the case, so add a log when they mismatch. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2026-05-18T22:13:42+00:00 Amber Lin Amber.Lin@amd.com 2026-03-23T18:19:04+00:00 urn:sha1:36c063e72fc2a53c02a4d96e81a14fef433a3948 suspend_all_sdma_gangs is supported in new MES firmware for gfx 12.1 Signed-off-by: Amber Lin <Amber.Lin@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michael Chen<michael.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2026-04-28T18:46:00+00:00 Amber Lin Amber.Lin@amd.com 2026-03-13T10:08:40+00:00 urn:sha1:eed95012c71ad887b3b524325c23dcbb1b6c16be When removing queues fails, KFD calls amdgpu_mes to detect and reset hung queues, then cleans up those hung queues in KFD. Suggested-by: Jonathan Kim <jonathan.kim@amd.com> Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2026-04-28T18:42:36+00:00 Amber Lin Amber.Lin@amd.com 2026-03-19T21:50:52+00:00 urn:sha1:ef94439908c9ccb4d856c99a102fd2a0b1ea1662 In a multi-XCC GPU, pass the master XCC's ID to amdgpu_mes_suspend, amdgpu_mes_resume, and detect_and_reset_hung_queues so the command will be sent to the matching master MES when the compute partition mode is not SPX. Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2026-04-17T19:41:14+00:00 Amber Lin Amber.Lin@amd.com 2026-03-13T09:53:46+00:00 urn:sha1:26bde9453b5312f504d37b6b695ef8a165e554d4 Create hung_queue_hqd_info structure and fill in hung queses information passed by MES, including queue type, pipe id, and queue id. Suggested-by: Jonathan Kim <jonathan.kim@amd.com> Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2026-04-17T19:41:14+00:00 Amber Lin Amber.Lin@amd.com 2026-03-13T09:35:55+00:00 urn:sha1:640482525554cc08370f2355be61b9fdf2b066d4 Identify hung queues by comparing doorbells shown in hqd_info from MES with doorbells stored in the driver to find matching queues. Suggested-by: Jonathan Kim <jonathan.kim@amd.com> Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2026-04-17T19:41:14+00:00 Amber Lin Amber.Lin@amd.com 2026-03-13T09:27:22+00:00 urn:sha1:a132fc9bc2f8b394a2f75947a0e1f5c22482a94c When allocate the hung queues memory, we need to take the number of queues into account for the worst hang case. Suggested-by: Jonathan Kim <jonathan.kim@amd.com> Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2026-01-27T23:02:06+00:00 Tvrtko Ursulin tvrtko.ursulin@igalia.com 2026-01-12T10:22:33+00:00 urn:sha1:f7e06786512e730f750138b1221b6342bcf07859 Commit cb17fff3a254 ("drm/amdgpu/mes: remove unused functions") removed most of the code using these IDRs but forgot to remove the struct members and init/destroy paths. There is also interrupt handling code in SDMA 5.0 and 5.2 which appears to be using it, but is is unreachable since nothing ever allocates the relevant IDR. We replace those with one time warnings just to avoid any functional difference, but it is also possible they should be removed. v2: also fix up gfx_v12_1.c and sdma_v7_1.c Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> References: cb17fff3a254 ("drm/amdgpu/mes: remove unused functions") Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2026-01-10T19:21:52+00:00 Lang Yu lang.yu@amd.com 2025-12-19T12:27:00+00:00 urn:sha1:0f744593adecfa12ce7c4bfc4a6c2850458c4e88 "adev->mes.compute_hqd_mask[i] = adev->gfx.disable_kq ? 0xF" is actually incorrect for MEC with 8 queues per pipe. Let's get rid of version check and hardcode, calculate hqd mask with number of queues per pipe and number of gfx/compute queues kernel used. Currently, only MEC1 is used for both kernel/user compute queue. To enable other MEC, we need to redistribute queues per pipe and adjust queue resource shared with kfd that needs a separate patch. Just skip other MEC for now to avoid potential issues. v2: Force reserved queues to 0 if kernel queue is explicitly disabled. Signed-off-by: Lang Yu <lang.yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2025-12-10T22:38:21+00:00 chong li chongli2@amd.com 2025-11-28T02:51:51+00:00 urn:sha1:f9f3240018e8f5b68bb791102d4736b5883d8aab v4: use func "amdgpu_gfx_get_hdp_flush_mask" to get ref_and_mask for gfx9 through gfx12. v3: Unify the get_ref_and_mask function in amdgpu_gfx_funcs, to support both GFX11 and earlier generations v2: place "get_ref_and_mask" in amdgpu_gfx_funcs instead of amdgpu_ring, since this function only assigns the cp entry. v1: both gfx ring and mes ring use cp0 to flush hdp, cause conflict. use function get_ref_and_mask to assign the cp entry. reassign mes to use cp8 instead. Signed-off-by: chong li <chongli2@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>