Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v7.0-rc7 2026-01-27T23:02:06+00:00 2026-01-27T23:02:06+00:00 Tvrtko Ursulin tvrtko.ursulin@igalia.com 2026-01-12T10:22:33+00:00 urn:sha1:f7e06786512e730f750138b1221b6342bcf07859 Commit cb17fff3a254 ("drm/amdgpu/mes: remove unused functions") removed most of the code using these IDRs but forgot to remove the struct members and init/destroy paths. There is also interrupt handling code in SDMA 5.0 and 5.2 which appears to be using it, but is is unreachable since nothing ever allocates the relevant IDR. We replace those with one time warnings just to avoid any functional difference, but it is also possible they should be removed. v2: also fix up gfx_v12_1.c and sdma_v7_1.c Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> References: cb17fff3a254 ("drm/amdgpu/mes: remove unused functions") Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2026-01-10T19:21:52+00:00 Lang Yu lang.yu@amd.com 2025-12-19T12:27:00+00:00 urn:sha1:0f744593adecfa12ce7c4bfc4a6c2850458c4e88 "adev->mes.compute_hqd_mask[i] = adev->gfx.disable_kq ? 0xF" is actually incorrect for MEC with 8 queues per pipe. Let's get rid of version check and hardcode, calculate hqd mask with number of queues per pipe and number of gfx/compute queues kernel used. Currently, only MEC1 is used for both kernel/user compute queue. To enable other MEC, we need to redistribute queues per pipe and adjust queue resource shared with kfd that needs a separate patch. Just skip other MEC for now to avoid potential issues. v2: Force reserved queues to 0 if kernel queue is explicitly disabled. Signed-off-by: Lang Yu <lang.yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2025-12-10T22:38:21+00:00 chong li chongli2@amd.com 2025-11-28T02:51:51+00:00 urn:sha1:f9f3240018e8f5b68bb791102d4736b5883d8aab v4: use func "amdgpu_gfx_get_hdp_flush_mask" to get ref_and_mask for gfx9 through gfx12. v3: Unify the get_ref_and_mask function in amdgpu_gfx_funcs, to support both GFX11 and earlier generations v2: place "get_ref_and_mask" in amdgpu_gfx_funcs instead of amdgpu_ring, since this function only assigns the cp entry. v1: both gfx ring and mes ring use cp0 to flush hdp, cause conflict. use function get_ref_and_mask to assign the cp entry. reassign mes to use cp8 instead. Signed-off-by: chong li <chongli2@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2025-12-08T19:25:58+00:00 Hawking Zhang Hawking.Zhang@amd.com 2025-05-06T06:43:36+00:00 urn:sha1:f364fb3cb40364e0c91ddc83bac90cfd09a5602b Configure a single mes instance if the xcc_mask remains uninitialized. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2025-12-08T18:56:29+00:00 Mukul Joshi mukul.joshi@amd.com 2025-03-24T22:59:23+00:00 urn:sha1:36b266bd3aad0698591c2c93a112e2dd6b6678f6 Generalize the calculation for determining the HQD mask and VMID mask passed to MES during initialization. v2: rebase (Alex) Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2025-12-08T18:56:29+00:00 Jack Xiao Jack.Xiao@amd.com 2024-11-21T08:22:38+00:00 urn:sha1:d09c7e266c8cd5590db59693ea3c3a66a55e63ab a. extend mes pipe instances to num_xcc * max_mes_pipe b. initialize mes schq/kiq pipes per xcc c. submit mes packet to mes ring according to xcc_id v2: rebase (Alex) Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2025-10-20T22:25:41+00:00 Victor Zhao Victor.Zhao@amd.com 2025-10-09T02:42:48+00:00 urn:sha1:6169b555db1392e79159e114fff105987231e4ce Currently SRIOV runtime will use kiq to write HDP_MEM_FLUSH_CNTL for hdp flush. This register need to be write from CPU for nbif to aware, otherwise it will not work. Implement amdgpu_kiq_hdp_flush and use kiq to do gpu hdp flush during sriov runtime. v2: - fallback to amdgpu_asic_flush_hdp when amdgpu_kiq_hdp_flush failed - add function amdgpu_mes_hdp_flush v3: - changed returned error Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2025-10-13T18:14:33+00:00 Alex Deucher alexander.deucher@amd.com 2025-10-06T18:23:59+00:00 urn:sha1:fb3c34ef49947631a4434c7157612d3c8114dfc2 The firmware limits the max vmid, but align the settings with the hw limits as well just to be safe. Reviewed-by: Shaoyun liu <Shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2025-10-13T18:14:28+00:00 Jonathan Kim jonathan.kim@amd.com 2025-06-05T14:18:37+00:00 urn:sha1:277bb0f83e98261018ddd82b7ab8154bb9b93237 Suspend/resume all gangs has been available for GFX12 for a while now so enable it. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2025-10-13T18:14:28+00:00 Jonathan Kim jonathan.kim@amd.com 2025-10-09T15:28:19+00:00 urn:sha1:0ef930e1faca6418316e5b9a3b4d1f6ae9e5b240 By design the MES will return an array result that is twice the number of hung doorbells it can report. i.e. if up k reported doorbells are supported, then the second half of the array, also of length k, holds the HQD information (type/queue/pipe) where queue 1 corresponds to index 0 and k, queue 2 corresponds to index 1 and k + 1 etc ... The driver will use the HDQ info to target queue/pipe reset for hardware scheduled user compute queues. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>