<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c, branch linux-4.13.y</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=linux-4.13.y</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=linux-4.13.y'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2017-05-24T21:41:31+00:00</updated>
<entry>
<title>drm/amdgpu: add a ring func for vcn start command</title>
<updated>2017-05-24T21:41:31+00:00</updated>
<author>
<name>Leo Liu</name>
<email>leo.liu@amd.com</email>
</author>
<published>2017-05-11T20:29:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ef44f8541e8e99f1040c0d1b147956e2c2f25d79'/>
<id>urn:sha1:ef44f8541e8e99f1040c0d1b147956e2c2f25d79</id>
<content type='text'>
Needed for the proper command sequence for VCN.

Signed-off-by: Leo Liu &lt;leo.liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: make pipeline sync be in same place v2</title>
<updated>2017-05-24T21:40:35+00:00</updated>
<author>
<name>Chunming Zhou</name>
<email>David1.Zhou@amd.com</email>
</author>
<published>2017-05-11T18:52:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=b9bf33d5ac55aa9f23b60b4d03017b2e59d02f02'/>
<id>urn:sha1:b9bf33d5ac55aa9f23b60b4d03017b2e59d02f02</id>
<content type='text'>
v2: directly return for 'if' case.

Signed-off-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add sched sync for amdgpu job v2</title>
<updated>2017-05-24T21:40:35+00:00</updated>
<author>
<name>Chunming Zhou</name>
<email>David1.Zhou@amd.com</email>
</author>
<published>2017-05-09T07:50:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=df83d1ebc9e304fa3ba4bf79dba76418789a77cf'/>
<id>urn:sha1:df83d1ebc9e304fa3ba4bf79dba76418789a77cf</id>
<content type='text'>
this is an improvement for previous patch, the sched_sync is to store fence
that could be skipped as scheduled, when job is executed, we didn't need
pipeline_sync if all fences in sched_sync are signalled, otherwise insert
pipeline_sync still.

v2: handle error when adding fence to sync failed.

Signed-off-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
Reviewed-by: Junwei Zhang &lt;Jerry.Zhang@amd.com&gt; (v1)
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu:cleanup flag not used</title>
<updated>2017-05-24T21:40:27+00:00</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2017-05-03T06:55:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=503bb31be42e3fea15c5e81bb2d84a0123438c85'/>
<id>urn:sha1:503bb31be42e3fea15c5e81bb2d84a0123438c85</id>
<content type='text'>
Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu:use FRAME_CNTL for new GFX ucode (v2)</title>
<updated>2017-05-24T21:40:26+00:00</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2017-05-01T10:09:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=3b4d68e993d941ec993660f10bacdfd556731dc7'/>
<id>urn:sha1:3b4d68e993d941ec993660f10bacdfd556731dc7</id>
<content type='text'>
AI affected:

CP/HW team requires KMD insert FRAME_CONTROL(end) after
the last IB and before the fence of this DMAframe.

this is to make sure the cache are flushed, and it's a must
change no matter MCBP/SR-IOV or bare-metal case because new
CP hw won't do the cache flush for each IB anymore, it just
leaves it to KMD now.

with this patch, certain MCBP hang issue when rendering
vulkan/chained-ib are resolved.

v2: drop gfx8 changes.  gfx8 is not affected (Alex)

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix dependency issue</title>
<updated>2017-05-10T17:23:53+00:00</updated>
<author>
<name>Chunming Zhou</name>
<email>David1.Zhou@amd.com</email>
</author>
<published>2017-05-09T05:39:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=30514decb27d45b98599612cb5d3e6a20ba733a5'/>
<id>urn:sha1:30514decb27d45b98599612cb5d3e6a20ba733a5</id>
<content type='text'>
The problem is that executing the jobs in the right order doesn't give you the right result
because consecutive jobs executed on the same engine are pipelined.
In other words job B does it buffer read before job A has written it's result.

Signed-off-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: split VMID management by VMHUB</title>
<updated>2017-04-28T21:32:18+00:00</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-04-06T15:52:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=7645670decdb677e2f415ff91609d31e5d4777d8'/>
<id>urn:sha1:7645670decdb677e2f415ff91609d31e5d4777d8</id>
<content type='text'>
This way GFX and MM won't fight for VMIDs any more.

Initially disabled since we need to stop flushing all HUBS
at the same time as well.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Andres Rodriguez &lt;andresx7@gmail.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Couple small warning fixes</title>
<updated>2017-03-30T03:55:48+00:00</updated>
<author>
<name>Harry Wentland</name>
<email>harry.wentland@amd.com</email>
</author>
<published>2017-03-28T15:29:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e51a3226d48fd02b37090a01c17587944743389a'/>
<id>urn:sha1:e51a3226d48fd02b37090a01c17587944743389a</id>
<content type='text'>
Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu:changes in gfx DMAframe scheme (v2)</title>
<updated>2017-03-30T03:55:42+00:00</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2017-03-15T04:18:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e9d672b2910a8d5e528d859dce9ad9baa748087a'/>
<id>urn:sha1:e9d672b2910a8d5e528d859dce9ad9baa748087a</id>
<content type='text'>
1) Adapt to vulkan:
Now use double SWITCH BUFFER to replace the 128 nops w/a,
because when vulkan introduced, umd can insert 7 ~ 16 IBs
per submit which makes 256 DW size cannot hold the whole
DMAframe (if we still insert those 128 nops), CP team suggests
use double SWITCH_BUFFERs, instead of tricky 128 NOPs w/a.

2) To fix the CE VM fault issue when MCBP introduced:
Need one more COND_EXEC wrapping IB part (original one us
for VM switch part).

this change can fix vm fault issue caused by below scenario
without this change:

&gt;CE passed original COND_EXEC (no MCBP issued this moment),
 proceed as normal.

&gt;DE catch up to this COND_EXEC, but this time MCBP issued,
 thus DE treats all following packages as NOP. The following
 VM switch packages now looks just as NOP to DE, so DE
 dosen't do VM flush at all.

&gt;Now CE proceeds to the first IBc, and triggers VM fault,
 because DE didn't do VM flush for this DMAframe.

3) change estimated alloc size for gfx9.
with new DMAframe scheme, we need modify emit_frame_size
for gfx9

4) No need to insert 128 nops after gfx8 vm flush anymore
because there was double SWITCH_BUFFER append to vm flush,
and for gfx7 we already use double SWITCH_BUFFER following
after vm_flush so no change needed for it.

5) Change emit_frame_size for gfx8

v2: squash in BUG removal from Monk

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add a ring func for end command</title>
<updated>2017-03-30T03:53:43+00:00</updated>
<author>
<name>Leo Liu</name>
<email>leo.liu@amd.com</email>
</author>
<published>2016-12-14T20:05:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=135d4735d8c5d8fa6c705657f5dd9d8d4193dcd1'/>
<id>urn:sha1:135d4735d8c5d8fa6c705657f5dd9d8d4193dcd1</id>
<content type='text'>
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Leo Liu &lt;leo.liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
