kernel/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h, branch v6.12.80

drm/amdgpu: Add address alignment support to DCC buffers

2024-08-07T22:23:42+00:00

Add address alignment support to the DCC VRAM buffers. v2: - adjust size based on the max_texture_channel_caches values only for GFX12 DCC buffers. - used AMDGPU_GEM_CREATE_GFX12_DCC flag to apply change only for DCC buffers. - roundup non power of two DCC buffer adjusted size to nearest power of two number as the buddy allocator does not support non power of two alignments. This applies only to the contiguous DCC buffers. v3:(Alex) - rewrite the max texture channel caches comparison code in an algorithmic way to determine the alignment size. v4:(Alex) - Move the logic from amdgpu_vram_mgr_dcc_alignment() to gmc_v12_0.c and add a new gmc func callback for dcc alignment. If the callback is non-NULL, call it to get the alignment, otherwise, use the default. v5:(Alex) - Set the Alignment to a default value if the callback doesn't exist. - Add the callback to amdgpu_gmc_funcs. v6: - Fix checkpatch warning reported by Intel CI. v7:(Christian) - remove the AMDGPU_GEM_CREATE_GFX12_DCC flag and keep a flag that checks the BO pinning and for a specific hw generation. v8:(Christian) - move this check into gmc_v12_0_get_dcc_alignment. v9: - Fix 32bit build errors Signed-off-by: Arunpravin Paneer Selvam Acked-by: Alex Deucher Acked-by: Christian König Reviewed-by: Frank Min Signed-off-by: Alex Deucher (cherry picked from commit aa94b623cb9233b91ed342dd87ecd62e56ff4938)

drm/amdgpu: Use NPS ranges from discovery table

2024-05-17T21:40:36+00:00

Add GMC API to fetch NPS range information from discovery table. Use NPS range information in GMC 9.4.3 SOCs when available, otherwise fallback to software method. Signed-off-by: Lijo Lazar Reviewed-by: Le Ma Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: move kiq_reg_write_reg_wait() out of amdgpu_virt.c

2024-01-15T23:35:36+00:00

It's used for more than just SR-IOV now, so move it to amdgpu_gmc.c and rename it to better match the functionality and update the comments in the code paths to better document when each path is used and why. No functional change. Reviewed-by: Shaoyun.liu Acked-by: Christian König Signed-off-by: Alex Deucher Cc: Shaoyun.Liu@amd.com Cc: Christian.Koenig@amd.com

drm/amdgpu/gmc: add a way to force a particular placement for GART

2023-10-04T22:36:07+00:00

We normally place GART based on the location of VRAM and the available address space around that, but provide an option to force a particular location for hardware that needs it. v2: Switch to passing the placement via parameter Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu/gmc: set a default disable value for AGP

2023-09-26T21:00:22+00:00

To disable AGP, the start needs to be set to a higher value than the end. Set a default disable value for the AGP aperture and allow the IP specific GMC code to enable it selectively be calling amdgpu_gmc_agp_location(). Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: drop error return from flush_gpu_tlb_pasid

2023-09-26T20:55:09+00:00

That function never fails, drop the error return. Signed-off-by: Christian König Reviewed-by: Alex Deucher Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher

drm/amdgpu: fix and cleanup gmc_v9_0_flush_gpu_tlb_pasid

2023-09-26T20:55:09+00:00

Testing for reset is pointless since the reset can start right after the test. The same PASID can be used by more than one VMID, invalidate each of them. Move the KIQ and all the workaround handling into common GMC code. Signed-off-by: Christian König Reviewed-by: Alex Deucher Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher

drm/amdgpu: rework gmc_v10_0_flush_gpu_tlb v2

2023-09-26T20:54:52+00:00

Move the SDMA workaround necessary for Navi 1x into a higher layer. v2: use dev_err Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: Update invalid PTE flag setting

2023-07-07T17:51:47+00:00

Update the invalid PTE flag setting with TF enabled. This is to ensure, in addition to transitioning the retry fault to a no-retry fault, it also causes the wavefront to enter the trap handler. With the current setting, the fault only transitions to a no-retry fault. Additionally, have 2 sets of invalid PTE settings, one for TF enabled, the other for TF disabled. The setting with TF disabled, doesn't work with TF enabled. Signed-off-by: Mukul Joshi Acked-by: Christian König Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher

drm/amdgpu: Update total channel number for umc v8_10

2023-06-15T15:06:59+00:00

Update total channel number for umc v8_10. Signed-off-by: Candice Li Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher