<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h, branch v6.1.168</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.1.168</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.1.168'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2022-08-16T22:14:31+00:00</updated>
<entry>
<title>drm/amdgpu: save and restore gc hub regs</title>
<updated>2022-08-16T22:14:31+00:00</updated>
<author>
<name>Victor Zhao</name>
<email>Victor.Zhao@amd.com</email>
</author>
<published>2022-06-21T08:59:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=bfaced6ee77484d8b9c6baf86a8e9406f80108c5'/>
<id>urn:sha1:bfaced6ee77484d8b9c6baf86a8e9406f80108c5</id>
<content type='text'>
Save and restore gfxhub regs as they will be reset during mode 2

Signed-off-by: Victor Zhao &lt;Victor.Zhao@amd.com&gt;
Acked-by: Andrey Grodzovsky &lt;andrey.grodzovsky@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: save the setting of VM_CONTEXT_CNTL</title>
<updated>2022-05-04T13:57:22+00:00</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2021-05-12T07:53:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d7dab4fc44ad020b48a893dae728190e2f01f14d'/>
<id>urn:sha1:d7dab4fc44ad020b48a893dae728190e2f01f14d</id>
<content type='text'>
MES firmware needs the setting of VM_CONTEXT_CNTL to perform
vmid switch. Save the initial setting when hub initializing.

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add mmhub v3_0 ip block</title>
<updated>2022-05-04T13:57:18+00:00</updated>
<author>
<name>Tianci.Yin</name>
<email>tianci.yin@amd.com</email>
</author>
<published>2020-10-12T10:10:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=98a0f8687e3135b4606e17bb05fc0a5fa33be55f'/>
<id>urn:sha1:98a0f8687e3135b4606e17bb05fc0a5fa33be55f</id>
<content type='text'>
Add support for mmhub v3.0

Signed-off-by: Tianci.Yin &lt;tianci.yin@amd.com&gt;
Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/discovery: store the number of UMC IPs on the asic</title>
<updated>2022-04-28T21:47:22+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2022-03-31T22:12:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=a2efebf1a4f8b2bb092668e1dabaa9981cd87af1'/>
<id>urn:sha1:a2efebf1a4f8b2bb092668e1dabaa9981cd87af1</id>
<content type='text'>
For chips with IP discovery get this from the table,
hardcode it for older asics.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: store the mall size in the gmc structure</title>
<updated>2022-04-28T21:47:16+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2022-03-31T22:11:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=053d35dedd7f2e0cb5e74ea8588aed09d6701d9c'/>
<id>urn:sha1:053d35dedd7f2e0cb5e74ea8588aed09d6701d9c</id>
<content type='text'>
This will be useful in future patches.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Merge get_reserved_allocation to get_vbios_allocations.</title>
<updated>2022-03-15T19:01:12+00:00</updated>
<author>
<name>Yongqiang Sun</name>
<email>yongqiang.sun@amd.com</email>
</author>
<published>2022-03-14T18:17:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=3f543552846b9ae47c8442af1c506207bdcc00d2'/>
<id>urn:sha1:3f543552846b9ae47c8442af1c506207bdcc00d2</id>
<content type='text'>
Some ASICs need reserved memory for firmware or other components,
which is not allowed to be used by driver.
amdgpu_gmc_get_reserved_allocation is to handle additional areas.
To avoid any missing calling,
merged amdgpu_gmc_get_reserved_allocation to
amdgpu_gmc_get_vbios_allocations.

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Yongqiang Sun &lt;yongqiang.sun@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Move xgmi ras initialization from .late_init to .early_init</title>
<updated>2022-01-25T23:00:33+00:00</updated>
<author>
<name>yipechai</name>
<email>YiPeng.Chai@amd.com</email>
</author>
<published>2022-01-18T09:59:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=1f33bd18d703ecdf7b664168d640439e867d1605'/>
<id>urn:sha1:1f33bd18d703ecdf7b664168d640439e867d1605</id>
<content type='text'>
Move xgmi ras initialization from .late_init to .early_init, which let
xgmi ras can be initialized only once.

Signed-off-by: yipechai &lt;YiPeng.Chai@amd.com&gt;
Reviewed-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add vram check function for GMC</title>
<updated>2022-01-20T03:31:51+00:00</updated>
<author>
<name>Xiaojian Du</name>
<email>Xiaojian.Du@amd.com</email>
</author>
<published>2022-01-17T04:44:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=479e3b02b73a2de2b19df2950863149c59d57bfe'/>
<id>urn:sha1:479e3b02b73a2de2b19df2950863149c59d57bfe</id>
<content type='text'>
This patch will add vram check function for GMC block.
It will write pattern data to the vram and then read back from the vram,
so that to verify the work status of vram.
This patch  will cover gmc v6/7/8/9/10.

Signed-off-by: Xiaojian Du &lt;Xiaojian.Du@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Modify xgmi block to fit for the unified ras block data and ops</title>
<updated>2022-01-14T22:51:59+00:00</updated>
<author>
<name>yipechai</name>
<email>YiPeng.Chai@amd.com</email>
</author>
<published>2022-01-04T10:56:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6c2453861f48e4e779cafa01c09e78ddc2c23c6b'/>
<id>urn:sha1:6c2453861f48e4e779cafa01c09e78ddc2c23c6b</id>
<content type='text'>
1.Modify gmc block to fit for the unified ras block data and ops.
2.Change amdgpu_xgmi_ras_funcs to amdgpu_xgmi_ras, and the corresponding variable name remove _funcs suffix.
3.Remove the const flag of gmc ras variable so that gmc ras block can be able to be inserted into amdgpu device ras block link list.
4.Invoke amdgpu_ras_register_ras_block function to register gmc ras block into amdgpu device ras block link list.
5.Remove the redundant code about gmc in amdgpu_ras.c after using the unified ras block.

Signed-off-by: yipechai &lt;YiPeng.Chai@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: John Clements &lt;john.clements@amd.com&gt;
Reviewed-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: handle IH ring1 overflow</title>
<updated>2021-12-01T21:03:34+00:00</updated>
<author>
<name>Philip Yang</name>
<email>Philip.Yang@amd.com</email>
</author>
<published>2021-11-18T20:24:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=3c2d6ea27955cfac8590884d207353eece8c2cee'/>
<id>urn:sha1:3c2d6ea27955cfac8590884d207353eece8c2cee</id>
<content type='text'>
IH ring1 is used to process GPU retry fault, overflow is enabled to
drain retry fault because we want receive other interrupts while
handling retry fault to recover range. There is no overflow flag set
when wptr pass rptr. Use timestamp of rptr and wptr to handle overflow
and drain retry fault.

If fault timestamp goes backward, the fault is filtered and should not
be processed. Drain fault is finished if processed_timestamp is equal to
or larger than checkpoint timestamp.

Add amdgpu_ih_functions interface decode_iv_ts for different chips to
get timestamp from IV entry with different iv size and timestamp offset.
amdgpu_ih_decode_iv_ts_helper is used for vega10, vega20, navi10.

Signed-off-by: Philip Yang &lt;Philip.Yang@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
