Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v5.15.7 2021-06-04T20:03:12+00:00 2021-06-04T20:03:12+00:00 Huang Rui ray.huang@amd.com 2020-12-16T09:21:27+00:00 urn:sha1:e15a5fb9b6ac2556a4fe59dba5faa34c695e8b73 Some ASICs such as Yellow Carp needs to reserve a region of video memory to avoid access from driver. So this patch is to introduce a stolen reserved buffer to protect specific buffer region. v2: free this buffer in amdgpu_ttm_fini. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-and-Tested-by: Aaron Liu <aaron.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2021-04-29T03:36:05+00:00 Philip Yang Philip.Yang@amd.com 2021-04-20T14:05:44+00:00 urn:sha1:36255b5f619594504e9d76de23b58e99c5e08ceb Add interface to remove address from fault filter ring by resetting fault ring entry key, then future vm fault on the address will be processed to recover. Define fault key as atomic64_t type to use atomic read/set/cmpxchg key to protect fault ring access by interrupt handler and interrupt deferred work for vg20. Change fault->timestamp to 48-bit to share same uint64_t with 8-bit fault->next, it is enough for 48bit IH timestamp. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2021-04-21T01:43:49+00:00 Oak Zeng Oak.Zeng@amd.com 2021-03-11T17:17:51+00:00 urn:sha1:5f41741a6d46b55f187e4314b767bb15e7e263d0 This reverts commit 2f055097daef498da57552f422f49de50a1573e6. 2f055097daef498da57552f422f49de50a1573e6 was a driver workaround when PSP firmware was not ready. Now the PSP fw is ready so we revert this driver workaround. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2021-04-15T20:02:54+00:00 Oak Zeng Oak.Zeng@amd.com 2021-04-01T19:36:40+00:00 urn:sha1:dead5e421ac437deb94ea18c423e898c70a807a5 Add one function to calculate BO's GPU physical address. And another function to calculate BO's CPU physical address. v2: Use functions vs macros (Christian) Use more proper function names (Christian) Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2021-04-09T20:51:07+00:00 Hawking Zhang Hawking.Zhang@amd.com 2021-03-18T12:18:19+00:00 urn:sha1:52137ca8526cdeceab7651c314ce68ac49963512 xgmi ras is not managed by gpu driver when gpu is connected to cpu through xgmi. move all xgmi ras functions to xgmi_ras_funcs so gpu driver only initializes xgmi ras functions when it manages xgmi ras. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2021-03-24T03:10:38+00:00 shaoyunl shaoyun.liu@amd.com 2021-02-16T17:50:42+00:00 urn:sha1:e3c1b0712fdb039d9139ac0910be9a658c9cb65e In passthrough configuration, hypervisior will trigger the SBR(Secondary bus reset) to the devices without sync to each other. This could cause device hang since for XGMI configuration, all the devices within the hive need to be reset at a limit time slot. This serial of patches try to solve this issue by co-operate with new SMU which will only do minimum house keeping to response the SBR request but don't do the real reset job and leave it to driver. Driver need to do the whole sw init and minimum HW init to bring up the SMU and trigger the reset(possibly BACO) on all the ASICs at the same time Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Acked-by: Andrey Grodzovsky andrey.grodzovsky@amd.com Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2021-03-24T02:59:04+00:00 Oak Zeng Oak.Zeng@amd.com 2021-02-03T17:09:02+00:00 urn:sha1:be0478e7b02a3f045be3f466d14a311145ba141f More accurate words are used to address a code review feedback Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2021-03-24T02:58:52+00:00 Oak Zeng Oak.Zeng@amd.com 2021-01-26T19:51:36+00:00 urn:sha1:2f055097daef498da57552f422f49de50a1573e6 With the 2-level gart page table, vram is squeezed into gart aperture and FB aperture is disabled. Therefore all VRAM virtual addresses are in the GART aperture. However currently PSP requires TMR addresses in FB aperture. So we need some design change at PSP FW level to support this 2-level gart table driver change. Right now this PSP FW support doesn't exist. To workaround this issue temporarily, FB aperture is added back and the gart aperture address is converted back to FB aperture for this PSP TMR address. Will revert it after we get a fix from PSP FW. v2: squash in tmr fix for other asics (Kevin) Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2021-03-24T02:58:44+00:00 Oak Zeng Oak.Zeng@amd.com 2020-09-18T03:53:54+00:00 urn:sha1:a2902c09c51db02eeffd77485c1340fdf4536af5 Add functions to allocate PDB0, map it for CPU access, and fill it. Those functions are only used for 2-level vmid0 page table construction Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2021-03-24T02:58:42+00:00 Oak Zeng Oak.Zeng@amd.com 2020-09-18T01:32:56+00:00 urn:sha1:7b454b3a34335381cb660864eb1e11077847c5db If use gart for FB translation, we will squeeze vram into sysvm aperture. This requires 2 level gart table. Add page table depth and page table block size parameters to gmc. This is prepare work to 2-level gart table construction Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Christian Konig <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>