kernel/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h, branch v6.6.134Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.1342023-09-11T22:16:31+00:00drm/amdgpu: Store CU info from all XCCs for GFX v9.4.32023-09-11T22:16:31+00:00Mukul Joshimukul.joshi@amd.com2023-08-25T15:59:09+00:00urn:sha1:97e3c6a853f2af9145daf0c6ca25bcdf55c759d4
Currently, we store CU info only for a single XCC assuming
that it is the same for all XCCs. However, that may not be
true. As a result, store CU info for all XCCs. This info is
later used for CU masking.
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: update gc_info v2_1 from discovery2023-08-31T21:53:19+00:00Le Male.ma@amd.com2023-08-14T10:37:28+00:00urn:sha1:46b55e25c94af1689636f4be1760fb0d9ddd8ae2
Several new fields are exposed in gc_info v2_1
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Shiwu Zhang <shiwu.zhang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: make mcbp a per device setting2023-06-30T17:12:14+00:00Alex Deucheralexander.deucher@amd.com2023-06-16T20:49:04+00:00urn:sha1:02ff519e99fc90f6c9aed50def1b6d65e20c1875
So we can selectively enable it on certain devices. No
intended functional change.
Reviewed-and-tested-by: Jiadong Zhu <Jiadong.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add RAS definitions for GFX2023-06-09T14:37:37+00:00Tao Zhoutao.zhou1@amd.com2023-02-07T10:30:55+00:00urn:sha1:77462ab8c62b0dc65261c042771efea44a111131
Add common GFX RAS definitions.
v2: remove instance from amdgpu_gfx_ras_reg_entry,
amdgpu_ras_err_status_reg_entry has already defined it.
v3: remove memory id definitions from amdgpu_gfx.h, they are
related to IP version.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add GFX RAS common function2023-06-09T14:37:26+00:00Tao Zhoutao.zhou1@amd.com2023-02-02T10:57:04+00:00urn:sha1:d78c71321ea963378cd3c5646ac6c6483d8d1a50
The common function can help reduce redundant code.
v2: remove xcp operation, only need to do RAS operations for all
instances.
v3: remove check for GFX RAS support, will be checked in higher level.
add amdgpu prefix for the function name.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add compute mode descriptor function2023-06-09T13:57:48+00:00Lijo Lazarlijo.lazar@amd.com2023-03-07T05:03:05+00:00urn:sha1:f9632096be49ed31e86541e3e79960e21e8f1578
Keep a helper function to get description of compute partition mode.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add auto mode for compute partition2023-06-09T13:57:27+00:00Lijo Lazarlijo.lazar@amd.com2023-02-13T13:56:18+00:00urn:sha1:570de94b9c5d93e1c5bc4e357946efb93c662da9
When auto mode is specified, driver will choose the right compute
partition mode.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Reviewed-by: Philip Yang <philip.yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Move memory partition query to gmc2023-06-09T13:56:50+00:00Lijo Lazarlijo.lazar@amd.com2023-01-31T07:09:49+00:00urn:sha1:b6f90baafe267a0705c5d9b1429c875d3c39fbc7
GMC block handles memory related information, it makes more sense to
keep memory partition functions in gmc block.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: correct the vmhub index when page fault occurs2023-06-09T13:50:30+00:00Le Male.ma@amd.com2022-12-09T11:44:05+00:00urn:sha1:98b2e9cad2279132e3aa4b9caf9164b2e35c1a52
The AMDGPU_GFXHUB was bind to each xcc in the logical order.
Thus convert the node_id to logical xcc_id to index the
correct AMDGPU_GFXHUB. And "node_id / 4" can get the correct
AMDGPU_MMHUB0 index.
Signed-off-by: Le Ma <le.ma@amd.com>
Tested-by: Asad kamal <asad.kamal@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Switch to SOC partition funcs2023-06-09T13:49:42+00:00Lijo Lazarlijo.lazar@amd.com2022-11-16T11:45:47+00:00urn:sha1:8e7fd19380f9187dae3ad18a61793b1752dfa097
For GFXv9.4.3, use SOC level partition switch implementation rather than
keeping them at GFX IP level. Change the exisiting implementation in
GFX IP for keeping partition mode and restrict it to only GFX related
switch.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>