kernel/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c, branch v4.18.14

drm/amdgpu: fix UBSAN: Undefined behaviour for amdgpu_fence.c

2018-06-27T19:33:19+00:00

Here is the UBSAN dump: [ 3.866656] index 2 is out of range for type 'amdgpu_uvd_inst [2]' [ 3.866693] Workqueue: events work_for_cpu_fn [ 3.866702] Call Trace: [ 3.866710] dump_stack+0x85/0xc5 [ 3.866719] ubsan_epilogue+0x9/0x40 [ 3.866727] __ubsan_handle_out_of_bounds+0x89/0x90 [ 3.866737] ? rcu_read_lock_sched_held+0x58/0x60 [ 3.866746] ? __kmalloc+0x26c/0x2d0 [ 3.866846] amdgpu_fence_driver_start_ring+0x259/0x280 [amdgpu] [ 3.866896] amdgpu_ring_init+0x12c/0x710 [amdgpu] [ 3.866906] ? sprintf+0x42/0x50 [ 3.866956] amdgpu_gfx_kiq_init_ring+0x1bc/0x3a0 [amdgpu] [ 3.867009] gfx_v8_0_sw_init+0x1ad3/0x2360 [amdgpu] [ 3.867062] ? smu7_init+0xec/0x160 [amdgpu] [ 3.867109] amdgpu_device_init+0x112c/0x1dc0 [amdgpu] 'ring->me' might be set as 2 with 'amdgpu_gfx_kiq_init_ring', that would cause out of range for 'amdgpu_uvd_inst[2]'. v2: simplified with ring type Signed-off-by: Leo Liu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu/vg20:Restruct uvd.inst to support multiple instances

2018-05-18T21:08:12+00:00

Vega20 has dual-UVD. Need add multiple instances support for uvd. Restruct uvd.inst, using uvd.inst[0] to replace uvd.inst->. Repurpose amdgpu_ring::me for instance index, and initialize to 0. There are no any logical changes here. Signed-off-by: James Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu/vg20:Restruct uvd to support multiple uvds

2018-05-18T21:08:12+00:00

Vega20 has dual-UVD. Need Restruct amdgpu_device::uvd to support multiple uvds. There are no any logical changes here. Signed-off-by: James Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: optionally do a writeback but don't invalidate TC for IB fences

2018-05-15T18:43:32+00:00

There is a new IB flag that enables this new behavior. Full invalidation is unnecessary for RELEASE_MEM and doesn't make sense when draw calls from two adjacent gfx IBs run in parallel. This will be the new default for Mesa. v2: bump the version Signed-off-by: Marek Olšák Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: drop compute ring timeout setting for non-sriov only (v2)

2018-04-03T17:52:56+00:00

Sriov still wants these error messags on timeout. So, for sriov use case, the timeout setting on compute rings is kept. -v2: clean the code Signed-off-by: Evan Quan Reviewed-by: Christian König Reviewed-by: Monk Liu Signed-off-by: Alex Deucher

drm/amdgpu: no job timeout setting on compute queues

2018-03-21T19:36:57+00:00

Under some heavy computing environment(e.g. dgemm test), it takes the asic over 10+ seconds to finish the dispatched job which will trigger the timeout. It's quite confusing although it does not seem to bring any real problems. As a quick workround, we choose to not enfoce the timeout setting on compute queues. Signed-off-by: Evan Quan Acked-by: Alex Deucher Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: rename amdgpu_gpu_recover

2017-12-18T15:59:58+00:00

add device to the name for consistency. Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: Simplify amdgpu_lockup_timeout usage.

2017-12-15T22:15:00+00:00

With introduction of amdgpu_gpu_recovery we don't need any more to rely on amdgpu_lockup_timeout == 0 for disabling GPU reset. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: Add gpu_recovery parameter

2017-12-15T22:14:50+00:00

Add new parameter to control GPU recovery procedure. v2: Add auto logic where reset is disabled for bare metal and enabled for SR-IOV. Allow forced reset from debugfs. Signed-off-by: Andrey Grodzovsky Reviewed-by: Christian König Signed-off-by: Alex Deucher

drm/amdgpu: no need with INT for fence polling

2017-12-12T19:50:00+00:00

We are polling so no need for INT. Signed-off-by: Monk Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher