kernel/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c, branch linux-5.9.yLinux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=linux-5.9.y2020-12-02T07:51:47+00:00drm/amd/amdgpu: fix null pointer in runtime pm2020-12-02T07:51:47+00:00Kenneth Fengkenneth.feng@amd.com2020-11-17T13:10:59+00:00urn:sha1:a68122a12934fa0e6dbf38481db705d9e307bd9c
commit 7acc79eb5f78d3d1aa5dd21fc0a0329f1b7f2be5 upstream.
fix the null pointer issue when runtime pm is triggered.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drm/amdgpu: correct the gpu reset handling for job != NULL case2020-11-05T10:51:49+00:00Evan Quanevan.quan@amd.com2020-10-15T06:57:46+00:00urn:sha1:58d6fa17fffb42b4f1a2b7c7c328f706394c6d82
commit 207ac684792560acdb9e06f9d707ebf63c84b0e0 upstream.
Current code wrongly treat all cases as job == NULL.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-and-tested-by: Jane Jian <Jane.Jian@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drm/amdgpu: No sysfs, not an error condition2020-11-05T10:51:22+00:00Luben Tuikovluben.tuikov@amd.com2020-09-16T17:03:50+00:00urn:sha1:b0cd0b466a97b518630d7e26371a7a6d89cb9c13
[ Upstream commit 5aea5327ea2ddf544cbeff096f45fc2319b0714e ]
Not being able to create amdgpu sysfs attributes
is not a fatal error warranting not to continue
to try to bring up the display. Thus, if we get
an error trying to create amdgpu sysfs attrs,
report it and continue on to try to bring up
a display.
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Acked-by: Slava Abramov <slava.abramov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drm/amdgpu: remove gpu_info fw support for sienna_cichlid etc.2020-09-29T21:07:06+00:00Jiansong ChenJiansong.Chen@amd.com2020-09-23T03:58:23+00:00urn:sha1:0c7014154d6397d6a35bf3759839207f1c702a42
Remove gpu_info fw support for sienna_cichlid etc., since the
information can be retrieved from discovery binary.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: fix PSP autoload twice in FLR2020-08-06T20:44:41+00:00Liu ChengZheChengZhe.Liu@amd.com2020-07-24T09:22:15+00:00urn:sha1:6b6124bb4a0b05fa9ac052e14dd7c37c42ab9297
Assigning false to block->status.hw overwrites PSP's previous
hardware status, which causes the PSP to Resume operation after
hardware init.
Remove this assignment and let the PSP execute Resume operation
when it is told to.
v2: Remove the braces.
v3: Modify the description.
Signed-off-by: Liu ChengZhe <ChengZhe.Liu@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: add DC support for navy flounder2020-07-15T17:27:26+00:00Bhawanpreet LakhaBhawanpreet.Lakha@amd.com2020-07-08T21:11:12+00:00urn:sha1:a6c5308f2a7ad2a79fb6fd60b52367c51434c04a
Plumb DC support for navy flounder through.
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: set asic family and ip blocks for navy_flounder2020-07-15T16:45:48+00:00Jiansong ChenJiansong.Chen@amd.com2020-02-10T07:08:53+00:00urn:sha1:41f446bf52f36b4c5875873f78389312d50b3cff
Add the asic family and IP blocks for navy flounder.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add navy_flounder gpu info firmware2020-07-15T16:45:43+00:00Jiansong ChenJiansong.Chen@amd.com2020-02-10T07:00:33+00:00urn:sha1:120eb83336098ec9cdd21e81b80ccd8232287110
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add navy_flounder asic type2020-07-15T16:45:39+00:00Jiansong ChenJiansong.Chen@amd.com2020-02-10T06:25:57+00:00urn:sha1:ddd8fbe77dadf6d889a7bbd0f82fc29093582d75
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: RAS emergency restart logic refine2020-07-15T16:41:47+00:00Wenhui ShengWenhui.Sheng@amd.com2020-07-13T07:14:30+00:00urn:sha1:bb5c7235eaafb4e2f957e9f0f71a187db5cf525a
If we are in RAS triggered situation and
BACO isn't support, emergency restart is needed,
and this code is only needed for some specific
cases(vega20 with given smu fw version).
After we add smu mode1 reset for sienna cichlid, we
need to share AMD_RESET_METHOD_MODE1 with psp mode1 reset,
so in amdgpu_device_gpu_recover, we need differentiate
which mode1 reset we are using, then decide if it's
a full reset and then decide if emergency restart is needed,
the logic will become much more complex.
After discussion with Hawking, move emergency restart logic
to an independent function.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>