<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c, branch v4.12.9</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v4.12.9</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v4.12.9'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2017-04-28T21:33:14+00:00</updated>
<entry>
<title>drm/amdgpu: fix deadlock of reservation between cs and gpu reset v2</title>
<updated>2017-04-28T21:33:14+00:00</updated>
<author>
<name>Chunming Zhou</name>
<email>David1.Zhou@amd.com</email>
</author>
<published>2017-04-27T07:13:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=10e709cb296c98424c03408d23e3addeddcd4088'/>
<id>urn:sha1:10e709cb296c98424c03408d23e3addeddcd4088</id>
<content type='text'>
the case could happen when gpu reset:
1. when gpu reset, cs can be continue until sw queue is full, then push job will wait with holding pd reservation.
2. gpu_reset routine will also need pd reservation to restore page table from their shadow.
3. cs is waiting for gpu_reset complete, but gpu reset is waiting for cs releases reservation.

v2: handle amdgpu_cs_submit error path.

Signed-off-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Junwei Zhang &lt;Jerry.Zhang@amd.com&gt;
Reviewed-by: Monk Liu &lt;monk.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix fence memory leak in wait_all_fence V2</title>
<updated>2017-04-07T19:15:45+00:00</updated>
<author>
<name>Chunming Zhou</name>
<email>David1.Zhou@amd.com</email>
</author>
<published>2017-04-07T09:05:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=32df87dff04833bbf53f1750f6c6048192ed29bf'/>
<id>urn:sha1:32df87dff04833bbf53f1750f6c6048192ed29bf</id>
<content type='text'>
V2: remove **array method, directly fence_put after fence wait.

Signed-off-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt;
Reviewed-by: Christian König &lt;chrstian.koenig@amd.com&gt;
Reviewed-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: use uintptr_t instead of unsigned long to store pointer</title>
<updated>2017-04-06T17:28:08+00:00</updated>
<author>
<name>Alex Xie</name>
<email>AlexBin.Xie@amd.com</email>
</author>
<published>2017-04-05T20:54:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f4e7c7c1b4ed4c28caf679bc94ca5aa096310c10'/>
<id>urn:sha1:f4e7c7c1b4ed4c28caf679bc94ca5aa096310c10</id>
<content type='text'>
Signed-off-by: Alex Xie &lt;AlexBin.Xie@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: use a 64bit interval tree for VM management v2</title>
<updated>2017-04-04T17:40:32+00:00</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2017-03-30T12:03:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=a9f87f6452543505108d7d9b36d948534ea28b0b'/>
<id>urn:sha1:a9f87f6452543505108d7d9b36d948534ea28b0b</id>
<content type='text'>
This only makes a difference for 32-bit systems. The idea is to have a
fixed virtual address space size with 4-level page tables and to
minimize differences between 32 and 64-bit systems.

v2: Update commit message.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Couple small warning fixes</title>
<updated>2017-03-30T03:55:48+00:00</updated>
<author>
<name>Harry Wentland</name>
<email>harry.wentland@amd.com</email>
</author>
<published>2017-03-28T15:29:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e51a3226d48fd02b37090a01c17587944743389a'/>
<id>urn:sha1:e51a3226d48fd02b37090a01c17587944743389a</id>
<content type='text'>
Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu:changes in gfx DMAframe scheme (v2)</title>
<updated>2017-03-30T03:55:42+00:00</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2017-03-15T04:18:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e9d672b2910a8d5e528d859dce9ad9baa748087a'/>
<id>urn:sha1:e9d672b2910a8d5e528d859dce9ad9baa748087a</id>
<content type='text'>
1) Adapt to vulkan:
Now use double SWITCH BUFFER to replace the 128 nops w/a,
because when vulkan introduced, umd can insert 7 ~ 16 IBs
per submit which makes 256 DW size cannot hold the whole
DMAframe (if we still insert those 128 nops), CP team suggests
use double SWITCH_BUFFERs, instead of tricky 128 NOPs w/a.

2) To fix the CE VM fault issue when MCBP introduced:
Need one more COND_EXEC wrapping IB part (original one us
for VM switch part).

this change can fix vm fault issue caused by below scenario
without this change:

&gt;CE passed original COND_EXEC (no MCBP issued this moment),
 proceed as normal.

&gt;DE catch up to this COND_EXEC, but this time MCBP issued,
 thus DE treats all following packages as NOP. The following
 VM switch packages now looks just as NOP to DE, so DE
 dosen't do VM flush at all.

&gt;Now CE proceeds to the first IBc, and triggers VM fault,
 because DE didn't do VM flush for this DMAframe.

3) change estimated alloc size for gfx9.
with new DMAframe scheme, we need modify emit_frame_size
for gfx9

4) No need to insert 128 nops after gfx8 vm flush anymore
because there was double SWITCH_BUFFER append to vm flush,
and for gfx7 we already use double SWITCH_BUFFER following
after vm_flush so no change needed for it.

5) Change emit_frame_size for gfx8

v2: squash in BUG removal from Monk

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu:fix the check in cs_ib_fill for SRIOV</title>
<updated>2017-03-30T03:55:34+00:00</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2017-03-27T07:14:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=65333e4429c60b8bbbb7a9213cb5612761499acd'/>
<id>urn:sha1:65333e4429c60b8bbbb7a9213cb5612761499acd</id>
<content type='text'>
1,the check is only appliable for SRIOV GFX engine.
2,use chunk_ib instead of ib.

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Ken Wang &lt;Qingqing.wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu:protect cs submit</title>
<updated>2017-03-30T03:55:33+00:00</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2017-03-08T07:51:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9a1b3af10d6268a98076a4397cb1d47c4713efc7'/>
<id>urn:sha1:9a1b3af10d6268a98076a4397cb1d47c4713efc7</id>
<content type='text'>
to prevent submit two or more IBs with PREEMPT flags.

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu:fix cs_ib_fill</title>
<updated>2017-03-30T03:55:32+00:00</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2017-03-28T03:00:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=2a9ceb8daab01a4ee27383e4d344e4a8b781c165'/>
<id>urn:sha1:2a9ceb8daab01a4ee27383e4d344e4a8b781c165</id>
<content type='text'>
should use chunk_ib instead of ib, otherwise the logic
is incorrect.

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Ken Wang &lt;Qingqing.wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: handle multi level PD updates V2</title>
<updated>2017-03-30T03:55:27+00:00</updated>
<author>
<name>Christian König</name>
<email>christian.koenig@amd.com</email>
</author>
<published>2016-10-12T13:13:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=194d2161131b35f9cd4cf3e355f2d7cd3b296898'/>
<id>urn:sha1:194d2161131b35f9cd4cf3e355f2d7cd3b296898</id>
<content type='text'>
Update all levels of the page directory.

V2:
a. sub level pdes always are written to incorrect place.
b. sub levels need to update regardless of parent updates.

Signed-off-by: Christian König &lt;christian.koenig@amd.com&gt; (V1)
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt; (V1)
Signed-off-by: Chunming Zhou &lt;David1.Zhou@amd.com&gt; (V2)
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt; (V2)
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
