kernel/linux.git/drivers/gpu/drm/amd/amdgpu/amdgpu.h, branch v5.15.3

drm/amdgpu: revert "Add autodump debugfs node for gpu reset v8"

2021-11-06T13:13:31+00:00

commit c8365dbda056578eebe164bf110816b1a39b4b7f upstream. This reverts commit 728e7e0cd61899208e924472b9e641dbeb0775c4. Further discussion reveals that this feature is severely broken and needs to be reverted ASAP. GPU reset can never be delayed by userspace even for debugging or otherwise we can run into in kernel deadlocks. Signed-off-by: Christian König Acked-by: Alex Deucher Acked-by: Nirmoy Das Signed-off-by: Alex Deucher Signed-off-by: Greg Kroah-Hartman

drm/amdgpu: handle the case of pci_channel_io_frozen only in amdgpu_pci_resume

2021-10-05T17:02:31+00:00

In current code, when a PCI error state pci_channel_io_normal is detectd, it will report PCI_ERS_RESULT_CAN_RECOVER status to PCI driver, and PCI driver will continue the execution of PCI resume callback report_resume by pci_walk_bridge, and the callback will go into amdgpu_pci_resume finally, where write lock is releasd unconditionally without acquiring such lock first. In this case, a deadlock will happen when other threads start to acquire the read lock. To fix this, add a member in amdgpu_device strucutre to cache pci_channel_state, and only continue the execution in amdgpu_pci_resume when it's pci_channel_io_frozen. Fixes: c9a6b82f45e2 ("drm/amdgpu: Implement DPC recovery") Suggested-by: Andrey Grodzovsky Signed-off-by: Guchun Chen Reviewed-by: Andrey Grodzovsky Signed-off-by: Alex Deucher

drm/amd/amdgpu: Increase HWIP_MAX_INSTANCE to 10

2021-09-14T20:14:41+00:00

Seems like newer cards can have even more instances now. Found by UBSAN: array-index-out-of-bounds in drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:318:29 index 8 is out of range for type 'uint32_t *[8]' Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1697 Cc: stable@vger.kernel.org Signed-off-by: Ernst Sjöstrand Signed-off-by: Alex Deucher

drm/amdgpu: Add driver infrastructure for MCA RAS

2021-08-24T19:36:18+00:00

Add MCA specific IP blocks targetting RAS features Reviewed-by: Hawking Zhang Signed-off-by: John Clements Signed-off-by: Alex Deucher

drm/amd/pm: drop the unnecessary intermediate percent-based transition

2021-08-16T19:35:56+00:00

Currently, the readout of fan speed pwm is transited into percent-based and then pwm-based. However, the transition into percent-based is totally unnecessary and make the final output less accurate. Signed-off-by: Evan Quan Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher

drm/amdgpu: create amdgpu_vkms (v4)

2021-08-06T01:17:58+00:00

Modify the VKMS driver into an api that dce_virtual can use to create virtual displays that obey drm's atomic modesetting api. v2: Made local functions static. v3: Switched vkms_output kzalloc for kcalloc. Cleanup patches by moving display mode fixes to this patch. v4: Update atomic_check and atomic_update to comply with new kms api. Signed-off-by: Ryan Taylor Reported-by: kernel test robot Suggested-by: Alex Deucher Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: Rename amdgpu_acpi_is_s0ix_supported

2021-07-27T16:04:26+00:00

Rename amdgpu_acpi_is_s0ix_supported to better explain functionality by renaming to amdgpu_acpi_is_s0ix_active Signed-off-by: Pratik Vishwakarma Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: split amdgpu_device_access_vram() into two small parts

2021-07-16T17:58:13+00:00

split amdgpu_device_access_vram() 1. amdgpu_device_mm_access(): using MM_INDEX/MM_DATA to access vram 2. amdgpu_device_aper_access(): using vram aperature to access vram (option) Signed-off-by: Kevin Wang Reviewed-by: Christian König Signed-off-by: Alex Deucher

amdgpu/nv.c - Optimize code for video codec support structure

2021-07-16T17:46:09+00:00

Optimized the code for codec info structure initialization Signed-off-by: Veerabadhran Gopalakrishnan Reviewed-by: James Zhu Signed-off-by: Alex Deucher

drm/amdgpu: Don't flush/invalidate HDP for APUs and A+A

2021-06-04T20:02:38+00:00

Integrate two generic functions to determine if HDP flush is needed for all Asics. Signed-off-by: Eric Huang Reviewed-by: Christian König Signed-off-by: Alex Deucher