kernel/linux.git/drivers/gpu/drm/amd/amdgpu/aldebaran.c, branch v6.12.80Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v6.12.802024-07-08T20:46:14+00:00drm/amdgpu: sysfs node disable query error count during gpu reset2024-07-08T20:46:14+00:00YiPeng ChaiYiPeng.Chai@amd.com2024-07-01T06:43:17+00:00urn:sha1:78347b651aa5be8b48462c48fee7e8302dcc5819
Sysfs node disable query error count during gpu reset.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Fix uninitialized variable warnings2024-04-26T21:22:39+00:00Ma JunJun.Ma2@amd.com2024-04-22T06:47:52+00:00urn:sha1:60c448439f3b5db9431e13f7f361b4074d0e8594
return 0 to avoid returning an uninitialized variable r
Signed-off-by: Ma Jun <Jun.Ma2@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Fix ecc irq enable/disable unpaired2024-01-03T15:30:49+00:00Stanley.YangStanley.Yang@amd.com2023-12-15T08:13:23+00:00urn:sha1:a32c6f7f5737cc7e31cd7ad5133f0d96fca12ea6
The ecc_irq is disabled while GPU mode2 reset suspending process,
but not be enabled during GPU mode2 reset resume process.
Changed from V1:
only do sdma/gfx ras_late_init in aldebaran_mode2_restore_ip
delete amdgpu_ras_late_resume function
Changed from V2:
check umc ras supported before put ecc_irq
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Use function for IP version check2023-09-20T16:23:28+00:00Lijo Lazarlijo.lazar@amd.com2023-09-11T08:18:11+00:00urn:sha1:4e8303cf2c4dd27374a16a8881ec1a1cd5baf86f
Use an inline function for version check. Gives more flexibility to
handle any format changes.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Use default reset method handler2023-09-11T21:10:25+00:00Lijo Lazarlijo.lazar@amd.com2023-09-06T11:18:38+00:00urn:sha1:ca7aa3bf31dc7539af950e7c99c330aa3e9b2a0b
When reset method is not passed in reset context, look for the handler
for default reset method. On Aldebaran, default reset method for SOCs
connected to CPU over XGMI is MODE2.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Tested-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Keep reset handlers shared2023-08-30T18:57:54+00:00Lijo Lazarlijo.lazar@amd.com2023-08-05T09:57:01+00:00urn:sha1:f8a499aed290667bd37011ad534c66320dc48257
Instead of maintaining a list per device, keep the reset handlers common
per ASIC family. A pointer to the list of handlers is maintained in
reset control.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Tested-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Avoid another list of reset devices2022-08-10T19:07:14+00:00Lijo Lazarlijo.lazar@amd.com2022-08-03T11:24:24+00:00urn:sha1:0a83bb35d8a6ff3d18c2772afe616780c23293a6
A list of devices to be reset is already created in
amdgpu_device_gpu_recover function. Creating another list with the
same nodes is incorrect and not supported in list_head. Instead, pass
the device list as part of reset context.
Fixes: 9e08564727fc (drm/amdgpu: Refactor mode2 reset logic for v13.0.2)
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Refactor mode2 reset logic for v13.0.22022-03-04T18:03:29+00:00Lijo Lazarlijo.lazar@amd.com2022-02-25T09:24:13+00:00urn:sha1:9e08564727fc7770b30715fb81348aee54fa50c3
Use IP version and refactor reset logic to apply to a list of devices.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/pm: do not expose implementation details to other blocks out of power2022-01-14T22:51:14+00:00Evan Quanevan.quan@amd.com2021-11-22T02:57:20+00:00urn:sha1:bc143d8b8387ff0a22e4ef8e2375e63aa24bc311
Those implementation details(whether swsmu supported, some ppt_funcs supported,
accessing internal statistics ...)should be kept internally. It's not a good
practice and even error prone to expose implementation details.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Enable RAS error injection after mode2 reset on Aldebaran2021-10-13T18:14:35+00:00Mukul Joshimukul.joshi@amd.com2021-09-20T19:29:23+00:00urn:sha1:a4967a1ebf1b9e68cc99ab666ece65733fffcac6
Add the missing call to re-enable RAS error injections on the Aldebaran
mode2 reset code path.
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>