Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v6.1.168 2022-08-30T20:37:14+00:00 2022-08-30T20:37:14+00:00 Hawking Zhang Hawking.Zhang@amd.com 2022-07-02T02:20:03+00:00 urn:sha1:f926464e59b7029b02d731a9f8a31419ff973ed3 All gc v11_0_3 registers in gcvml2 range have different register offset from the ones in gc v11_0_0. v11_0_3 imu_rlc_ram programming has to be separated from v11_0_0 implementation v2: fix checkpatch errors (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Yang Wang <KevinYang.Wang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-08-30T20:36:54+00:00 Yang Wang KevinYang.Wang@amd.com 2022-07-01T09:19:27+00:00 urn:sha1:9436ac31c73526b1e070c050ee83c3870125bf82 add gfxhub_v3_0_3 support Signed-off-by: Yang Wang <KevinYang.Wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-08-16T22:14:31+00:00 Victor Zhao Victor.Zhao@amd.com 2022-07-28T02:44:47+00:00 urn:sha1:672c0218e3e22ccaeb2911da8d3b784d3b6cc1d8 To meet the requirement for multi container usecase which needs a quicker reset and not causing VRAM lost, adding the Mode2 reset handler for sienna_cichlid. v2: move skip mode2 flag part separately v3: remove the use of asic_reset_res Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-07-29T19:24:38+00:00 Xiaojian Du Xiaojian.Du@amd.com 2022-07-27T07:52:33+00:00 urn:sha1:7e8a3ca972adfc89609718c931577a86c494967b This patch will enable support for psp 13.0.4 blcok. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-07-18T20:37:47+00:00 YiPeng Chai YiPeng.Chai@amd.com 2022-07-04T09:18:14+00:00 urn:sha1:e4b1edf48fa37cf4f5ca403e384731fe28d13691 1. Support query umc ras error counter. 2. Support ras umc ue error address remapping. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-06-03T20:44:15+00:00 Huang Rui ray.huang@amd.com 2022-05-12T08:13:07+00:00 urn:sha1:10c4ad3ae025dd0e343a09d2ea4b0e71f8d10797 This adds mmhub v3_0_1 ip block support v2: rebase (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-05-10T21:53:11+00:00 Likun Gao Likun.Gao@amd.com 2022-05-05T17:57:30+00:00 urn:sha1:1b491330421bb0fdeff8eb928ce83fdd636087d3 Add Light SDMA (LSDMA) block and related function. LSDMA is a small instance of SDMA mainly for kernel driver use. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-05-06T20:57:36+00:00 James Zhu James.Zhu@amd.com 2022-05-03T16:18:49+00:00 urn:sha1:60a2e9eecf1676e3d59f050e5c9688830d7425cc Add common vcn sofware ring decode. v2: fixed compiling error Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Christian Koenig <Christian.Koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-05-06T14:36:13+00:00 Xiaojian Du Xiaojian.Du@amd.com 2021-12-14T08:16:33+00:00 urn:sha1:78039df8e8d24aa62611941b2d7e566c7020e729 This patch is to add the files of HDP v5.2 block. HDP (Host Data Port) is the IP which handles host access to VRAM via the PCI BAR. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-05-06T14:36:13+00:00 Xiaojian Du Xiaojian.Du@amd.com 2021-12-14T08:14:48+00:00 urn:sha1:810ecd40015c25b315b8cada7e86bfe2a7b55741 This patch is to add the files of NBIO v7.7 block. NBIO (New Bus IO) is the block which handles the GPU interface to the PCIe bus. v2: squash in register name fix (Xiaojian) Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>