kernel/linux.git/drivers/fpga/Makefile, branch v6.12.80

fpga: xilinx-selectmap: add new driver

2024-03-31T14:44:21+00:00

Xilinx 7 series FPGA can be programmed using a parallel port named the SelectMAP interface in the datasheet. This interface is compatible with the i.MX6 EIM bus controller but other types of external memory mapped parallel bus might work. xilinx-selectmap currently only supports the x8 mode where data is loaded at one byte per rising edge of the clock, with the MSb of each byte presented to the D0 pin. Signed-off-by: Charles Perry [yilun.xu@linux.intel.com: replace data type of i from u32 to size_t] Acked-by: Xu Yilun Link: https://lore.kernel.org/r/20240321220447.3260065-4-charles.perry@savoirfairelinux.com Signed-off-by: Xu Yilun

fpga: xilinx-spi: extract a common driver core

2024-03-31T14:41:26+00:00

Factor out the gpio handshaking (using PROGRAM_B, INIT_B and DONE) protocol in xilinx-core so that it can be reused for another driver. This commit does not change anything functionally to xilinx-spi. xilinx-core expects drivers to provide a write(const char* buf, size_t count) function that performs the actual write to the device, as well as a struct device* for resource management. Signed-off-by: Charles Perry Acked-by: Xu Yilun Link: https://lore.kernel.org/r/20240321220447.3260065-2-charles.perry@savoirfairelinux.com Signed-off-by: Xu Yilun

fpga: add configuration for the FPGA KUnit test suites.

2023-07-23T06:04:50+00:00

Add configuration for the KUnit test suites for the core components of the FPGA subsystem. Signed-off-by: Marco Pagani Acked-by: Xu Yilun Link: https://lore.kernel.org/r/20230718130304.87048-5-marpagan@redhat.com Signed-off-by: Xu Yilun

fpga: lattice-sysconfig-spi: add Lattice sysCONFIG FPGA manager

2022-10-25T06:44:03+00:00

Add support to the FPGA manager for programming Lattice ECP5 FPGA over slave SPI sysCONFIG interface. sysCONFIG interface core functionality is separate from both ECP5 and SPI specifics, so support for other FPGAs with different port types can be added in the future. Signed-off-by: Ivan Bornyakov Acked-by: Xu Yilun Link: https://lore.kernel.org/r/20221025053947.2737-2-i.bornyakov@metrotek.ru [yilun.xu@intel.com: remove redundant blank line after kmemdup] Signed-off-by: Xu Yilun

fpga: microchip-spi: add Microchip MPF FPGA manager

2022-06-24T04:12:31+00:00

Add support to the FPGA manager for programming Microchip Polarfire FPGAs over slave SPI interface with .dat formatted bitsream image. Signed-off-by: Ivan Bornyakov Reviewed-by: Conor Dooley Tested-by: Conor Dooley Acked-by: Xu Yilun Link: https://lore.kernel.org/r/20220623163248.3672-4-i.bornyakov@metrotek.ru Signed-off-by: Xu Yilun

fpga: m10bmc-sec: create max10 bmc secure update

2022-06-08T09:04:37+00:00

Create a sub-driver for the FPGA Card BMC in order to support secure updates. This patch creates the Max10 BMC Secure Update driver and provides sysfs files for displaying the root entry hashes (REH) for the FPGA static region (SR), the FPGA Partial Reconfiguration (PR) region, and the card BMC. The Intel MAX10 BMC Root of Trust (RoT) requires that all BMC Nios firmware and FPGA images are authenticated using ECDSA before loading and executing on the card. Code Signing Keys (CSK) are used to sign images. CSKs are signed by a root key. The root entry hash is created from the root public key. The RoT provides authentication by storing an REH bitstream to a write-once location. Image signatures are verified against the hash. Reviewed-by: Tom Rix Tested-by: Tianfei Zhang Signed-off-by: Russ Weight Link: https://lore.kernel.org/r/20220606160038.846236-3-russell.h.weight@intel.com Signed-off-by: Xu Yilun

fpga: Use tab instead of space indentation

2022-05-10T08:04:50+00:00

In FPGA Makefile has both space and tab indentation, to make them align use tab instead of space indentation. Signed-off-by: Nava kishore Manne Link: https://lore.kernel.org/r/20220423170235.2115479-5-nava.manne@xilinx.com Signed-off-by: Xu Yilun

fpga: versal-fpga: Add versal fpga manager driver

2021-07-21T11:14:09+00:00

Add support for Xilinx Versal FPGA manager. PDI source type can be DDR, OCM, QSPI flash etc.. But driver allocates memory always from DDR, Since driver supports only DDR source type. Reviewed-by: Moritz Fischer Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Nava kishore Manne Link: https://lore.kernel.org/r/20210626155248.5004-6-nava.manne@xilinx.com Signed-off-by: Greg Kroah-Hartman

fpga: dfl: add support for N3000 Nios private feature

2021-01-07T14:21:27+00:00

This patch adds support for the Nios handshake private feature on Intel PAC (Programmable Acceleration Card) N3000. The Nios is the embedded processor on the FPGA card. This private feature provides a handshake interface to FPGA Nios firmware, which receives retimer configuration command from host and executes via an internal SPI master (spi-altera). When Nios finishes the configuration, host takes over the ownership of the SPI master to control an Intel MAX10 BMC (Board Management Controller) Chip on the SPI bus. For Nios firmware handshake part, this driver requests the retimer configuration for Nios firmware on probe, and adds some sysfs nodes for user to query the onboard retimer's working mode and Nios firmware version. For SPI part, this driver adds a spi-altera platform device as well as the MAX10 BMC spi slave info. A spi-altera driver will be matched to handle the following SPI work. [mdf@kernel.org: Fixed up ABI doc kernel release] Reviewed-by: Tom Rix Signed-off-by: Xu Yilun Signed-off-by: Wu Hao Signed-off-by: Matthew Gerlach Signed-off-by: Russ Weight Signed-off-by: YueHaibing Link: https://lore.kernel.org/r/20210107043714.991646-8-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman

fpga: dfl: fme: add performance reporting support

2020-04-28T13:49:28+00:00

This patch adds support for performance reporting private feature for FPGA Management Engine (FME). Now it supports several different performance counters, including 'basic', 'cache', 'fabric', 'vtd' and 'vtd_sip'. It allows user to use standard linux tools to access these performance counters. e.g. List all events by "perf list" perf list | grep fme dfl_fme0/cache_read_hit/ [Kernel PMU event] dfl_fme0/cache_read_miss/ [Kernel PMU event] ... dfl_fme0/fab_mmio_read/ [Kernel PMU event] dfl_fme0/fab_mmio_write/ [Kernel PMU event] ... dfl_fme0/fab_port_mmio_read,portid=?/ [Kernel PMU event] dfl_fme0/fab_port_mmio_write,portid=?/ [Kernel PMU event] ... dfl_fme0/vtd_port_devtlb_1g_fill,portid=?/ [Kernel PMU event] dfl_fme0/vtd_port_devtlb_2m_fill,portid=?/ [Kernel PMU event] ... dfl_fme0/vtd_sip_iotlb_1g_hit/ [Kernel PMU event] dfl_fme0/vtd_sip_iotlb_1g_miss/ [Kernel PMU event] ... dfl_fme0/clock [Kernel PMU event] ... e.g. check increased counter value after run one application using "perf stat" command. perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_mmio_write/ ./test Performance counter stats for './test': 1 dfl_fme0/fab_mmio_read/ 2 dfl_fme0/fab_mmio_write/ 1.009496520 seconds time elapsed Please note that fabric counters support both fab_* and fab_port_*, but actually they are sharing one set of performance counters in hardware. If user wants to monitor overall data events on fab_* then fab_port_* can't be supported at the same time, see example below: perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_port_mmio_write,portid=0/ Performance counter stats for 'system wide': 0 dfl_fme0/fab_mmio_read/ dfl_fme0/fab_port_mmio_write,portid=0/ 2.141064085 seconds time elapsed Signed-off-by: Luwei Kang Signed-off-by: Xu Yilun Signed-off-by: Wu Hao Link: https://lore.kernel.org/r/1587949583-12058-3-git-send-email-hao.wu@intel.com Signed-off-by: Greg Kroah-Hartman