<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/fpga/Kconfig, branch v6.18.21</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.18.21</id>
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<updated>2024-03-31T14:44:21+00:00</updated>
<entry>
<title>fpga: xilinx-selectmap: add new driver</title>
<updated>2024-03-31T14:44:21+00:00</updated>
<author>
<name>Charles Perry</name>
<email>charles.perry@savoirfairelinux.com</email>
</author>
<published>2024-03-21T22:04:35+00:00</published>
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<id>urn:sha1:104712a0866f7e3eb050271fc104c543aac642e8</id>
<content type='text'>
Xilinx 7 series FPGA can be programmed using a parallel port named
the SelectMAP interface in the datasheet. This interface is compatible
with the i.MX6 EIM bus controller but other types of external memory
mapped parallel bus might work.

xilinx-selectmap currently only supports the x8 mode where data is loaded
at one byte per rising edge of the clock, with the MSb of each byte
presented to the D0 pin.

Signed-off-by: Charles Perry &lt;charles.perry@savoirfairelinux.com&gt;
[yilun.xu@linux.intel.com: replace data type of i from u32 to size_t]
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Link: https://lore.kernel.org/r/20240321220447.3260065-4-charles.perry@savoirfairelinux.com
Signed-off-by: Xu Yilun &lt;yilun.xu@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>fpga: xilinx-spi: extract a common driver core</title>
<updated>2024-03-31T14:41:26+00:00</updated>
<author>
<name>Charles Perry</name>
<email>charles.perry@savoirfairelinux.com</email>
</author>
<published>2024-03-21T22:04:33+00:00</published>
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<id>urn:sha1:a52e3a9dba347134ee53ebfe68b7b22548a387b0</id>
<content type='text'>
Factor out the gpio handshaking (using PROGRAM_B, INIT_B and DONE)
protocol in xilinx-core so that it can be reused for another driver.
This commit does not change anything functionally to xilinx-spi.

xilinx-core expects drivers to provide a write(const char* buf,
size_t count) function that performs the actual write to the device,
as well as a struct device* for resource management.

Signed-off-by: Charles Perry &lt;charles.perry@savoirfairelinux.com&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Link: https://lore.kernel.org/r/20240321220447.3260065-2-charles.perry@savoirfairelinux.com
Signed-off-by: Xu Yilun &lt;yilun.xu@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>fpga: add configuration for the FPGA KUnit test suites.</title>
<updated>2023-07-23T06:04:50+00:00</updated>
<author>
<name>Marco Pagani</name>
<email>marpagan@redhat.com</email>
</author>
<published>2023-07-18T13:03:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=3969f6458f783d2b4b8b15bef1eeab674eaa34bd'/>
<id>urn:sha1:3969f6458f783d2b4b8b15bef1eeab674eaa34bd</id>
<content type='text'>
Add configuration for the KUnit test suites for the core components
of the FPGA subsystem.

Signed-off-by: Marco Pagani &lt;marpagan@redhat.com&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Link: https://lore.kernel.org/r/20230718130304.87048-5-marpagan@redhat.com
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</content>
</entry>
<entry>
<title>mfd: intel-m10-bmc: Split into core and spi specific parts</title>
<updated>2023-01-27T10:35:00+00:00</updated>
<author>
<name>Ilpo Järvinen</name>
<email>ilpo.jarvinen@linux.intel.com</email>
</author>
<published>2023-01-16T10:08:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=603aed8ffd4c9cb633c05a514cfb5e8ca6b0751d'/>
<id>urn:sha1:603aed8ffd4c9cb633c05a514cfb5e8ca6b0751d</id>
<content type='text'>
Split the common code from intel-m10-bmc driver into intel-m10-bmc-core
and move the SPI bus parts into an interface specific file.

intel-m10-bmc-core becomes the core MFD functions which can support
multiple bus interface like SPI bus.

Co-developed-by: Tianfei zhang &lt;tianfei.zhang@intel.com&gt;
Signed-off-by: Tianfei zhang &lt;tianfei.zhang@intel.com&gt;
Reviewed-by: Russ Weight &lt;russell.h.weight@intel.com&gt;
Acked-by: Guenter Roeck &lt;linux@roeck-us.net&gt; # hwmon
Reviewed-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Signed-off-by: Ilpo Järvinen &lt;ilpo.jarvinen@linux.intel.com&gt;
Signed-off-by: Lee Jones &lt;lee@kernel.org&gt;
Link: https://lore.kernel.org/r/20230116100845.6153-5-ilpo.jarvinen@linux.intel.com
</content>
</entry>
<entry>
<title>Merge tag 'char-misc-6.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc</title>
<updated>2022-12-16T11:49:24+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2022-12-16T11:49:24+00:00</published>
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<id>urn:sha1:ba54ff1fb662215de683777f815b9e96276d55cf</id>
<content type='text'>
Pull char/misc driver updates from Greg KH:
 "Here is the large set of char/misc and other driver subsystem changes
  for 6.2-rc1. Nothing earth-shattering in here at all, just a lot of
  new driver development and minor fixes.

  Highlights include:

   - fastrpc driver updates

   - iio new drivers and updates

   - habanalabs driver updates for new hardware and features

   - slimbus driver updates

   - speakup module parameters added to aid in boot time configuration

   - i2c probe_new conversions for lots of different drivers

   - other small driver fixes and additions

  One semi-interesting change in here is the increase of the number of
  misc dynamic minors available to 1048448 to handle new huge-cpu
  systems.

  All of these have been in linux-next for a while with no reported
  problems"

* tag 'char-misc-6.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (521 commits)
  extcon: usbc-tusb320: Convert to i2c's .probe_new()
  extcon: rt8973: Convert to i2c's .probe_new()
  extcon: fsa9480: Convert to i2c's .probe_new()
  extcon: max77843: Replace irqchip mask_invert with unmask_base
  chardev: fix error handling in cdev_device_add()
  mcb: mcb-parse: fix error handing in chameleon_parse_gdd()
  drivers: mcb: fix resource leak in mcb_probe()
  coresight: etm4x: fix repeated words in comments
  coresight: cti: Fix null pointer error on CTI init before ETM
  coresight: trbe: remove cpuhp instance node before remove cpuhp state
  counter: stm32-lptimer-cnt: fix the check on arr and cmp registers update
  misc: fastrpc: Add dma_mask to fastrpc_channel_ctx
  misc: fastrpc: Add mmap request assigning for static PD pool
  misc: fastrpc: Safekeep mmaps on interrupted invoke
  misc: fastrpc: Add support for audiopd
  misc: fastrpc: Rework fastrpc_req_munmap
  misc: fastrpc: Use fastrpc_map_put in fastrpc_map_create on fail
  misc: fastrpc: Add fastrpc_remote_heap_alloc
  misc: fastrpc: Add reserved mem support
  misc: fastrpc: Rename audio protection domain to root
  ...
</content>
</entry>
<entry>
<title>fpga: m10bmc-sec: Fix kconfig dependencies</title>
<updated>2022-11-15T13:46:58+00:00</updated>
<author>
<name>Russ Weight</name>
<email>russell.h.weight@intel.com</email>
</author>
<published>2022-11-15T00:11:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=dfd10332596ef11ceafd29c4e21b4117be423fc4'/>
<id>urn:sha1:dfd10332596ef11ceafd29c4e21b4117be423fc4</id>
<content type='text'>
The secure update driver depends on the firmware-upload functionality of
the firmware-loader. The firmware-loader is carried in the firmware-class
driver which is enabled with the tristate CONFIG_FW_LOADER option. The
firmware-upload functionality is included in the firmware-class driver if
the bool FW_UPLOAD config is set.

The current dependency statement, "depends on FW_UPLOAD", is not adequate
because it does not implicitly turn on FW_LOADER. Instead of adding a
dependency, follow the convention used by drivers that require the
FW_LOADER_USER_HELPER functionality of the firmware-loader by using
select for both FW_LOADER and FW_UPLOAD.

Fixes: bdf86d0e6ca3 ("fpga: m10bmc-sec: create max10 bmc secure update")
Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Cc: stable@vger.kernel.org
Signed-off-by: Russ Weight &lt;russell.h.weight@intel.com&gt;
Acked-by: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Link: https://lore.kernel.org/r/20221115001127.289890-1-russell.h.weight@intel.com
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</content>
</entry>
<entry>
<title>fpga: lattice-sysconfig-spi: add Lattice sysCONFIG FPGA manager</title>
<updated>2022-10-25T06:44:03+00:00</updated>
<author>
<name>Ivan Bornyakov</name>
<email>i.bornyakov@metrotek.ru</email>
</author>
<published>2022-10-25T05:39:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=463dd43bc976d1dfaba5cd46b2a10addf8d3b4de'/>
<id>urn:sha1:463dd43bc976d1dfaba5cd46b2a10addf8d3b4de</id>
<content type='text'>
Add support to the FPGA manager for programming Lattice ECP5 FPGA over
slave SPI sysCONFIG interface.

sysCONFIG interface core functionality is separate from both ECP5 and
SPI specifics, so support for other FPGAs with different port types can
be added in the future.

Signed-off-by: Ivan Bornyakov &lt;i.bornyakov@metrotek.ru&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Link: https://lore.kernel.org/r/20221025053947.2737-2-i.bornyakov@metrotek.ru
[yilun.xu@intel.com: remove redundant blank line after kmemdup]
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</content>
</entry>
<entry>
<title>fpga: microchip-spi: add Microchip MPF FPGA manager</title>
<updated>2022-06-24T04:12:31+00:00</updated>
<author>
<name>Ivan Bornyakov</name>
<email>i.bornyakov@metrotek.ru</email>
</author>
<published>2022-06-23T16:32:46+00:00</published>
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<id>urn:sha1:5f8d4a9008307e0bf210906948953386935d361c</id>
<content type='text'>
Add support to the FPGA manager for programming Microchip Polarfire
FPGAs over slave SPI interface with .dat formatted bitsream image.

Signed-off-by: Ivan Bornyakov &lt;i.bornyakov@metrotek.ru&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Tested-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Acked-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
Link: https://lore.kernel.org/r/20220623163248.3672-4-i.bornyakov@metrotek.ru
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</content>
</entry>
<entry>
<title>fpga: m10bmc-sec: create max10 bmc secure update</title>
<updated>2022-06-08T09:04:37+00:00</updated>
<author>
<name>Russ Weight</name>
<email>russell.h.weight@intel.com</email>
</author>
<published>2022-06-06T16:00:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=bdf86d0e6ca307de8c85e9363b31ca8c86c0b0c7'/>
<id>urn:sha1:bdf86d0e6ca307de8c85e9363b31ca8c86c0b0c7</id>
<content type='text'>
Create a sub-driver for the FPGA Card BMC in order to support secure
updates.  This patch creates the Max10 BMC Secure Update driver and
provides sysfs files for displaying the root entry hashes (REH) for the
FPGA static region (SR), the FPGA Partial Reconfiguration (PR) region,
and the card BMC.

The Intel MAX10 BMC Root of Trust (RoT) requires that all BMC Nios firmware
and FPGA images are authenticated using ECDSA before loading and executing
on the card. Code Signing Keys (CSK) are used to sign images. CSKs are
signed by a root key. The root entry hash is created from the root public
key.

The RoT provides authentication by storing an REH bitstream to a write-once
location. Image signatures are verified against the hash.

Reviewed-by: Tom Rix &lt;trix@redhat.com&gt;
Tested-by: Tianfei Zhang &lt;tianfei.zhang@intel.com&gt;
Signed-off-by: Russ Weight &lt;russell.h.weight@intel.com&gt;
Link: https://lore.kernel.org/r/20220606160038.846236-3-russell.h.weight@intel.com
Signed-off-by: Xu Yilun &lt;yilun.xu@intel.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'fpga-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga into char-misc-next</title>
<updated>2021-08-05T12:26:03+00:00</updated>
<author>
<name>Greg Kroah-Hartman</name>
<email>gregkh@linuxfoundation.org</email>
</author>
<published>2021-08-05T12:26:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=72674e86b6fe2f656c93564635b675bcdf012844'/>
<id>urn:sha1:72674e86b6fe2f656c93564635b675bcdf012844</id>
<content type='text'>
Moritz writes:

FPGA Manager changes for 5.15-rc1

FPGA Manager

- Colin's change is a simple spelling cleanup.

DFL

- Martin's fist change exposes DFL feature revision to client drivers
- Martin's second change modifies a SPI driver to populate different
  spi_board_info modaliases based on the DFL feature revision

All patches have been reviewed on the mailing list, and have been in the
last few linux-next releases (as part of my for-next branch) without issues.

Signed-off-by: Moritz Fischer &lt;mdf@kernel.org&gt;

* tag 'fpga-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga:
  spi: spi-altera-dfl: support n5010 feature revision
  fpga: dfl: expose feature revision from struct dfl_device
  fpga: Fix spelling mistake "eXchnage" -&gt; "exchange" in Kconfig
</content>
</entry>
</feed>
