kernel/linux.git/drivers/edac/Kconfig, branch v6.6.133

EDAC/npcm: Add NPCM memory controller driver

2023-06-12T13:14:10+00:00

Add driver for memory controller present on Nuvoton NPCM SoCs. The memory controller supports single bit error correction and double bit error detection. Signed-off-by: Marvin Lin Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/r/20230111093245.318745-4-milkfafa@gmail.com

EDAC/zynqmp: Add EDAC support for Xilinx ZynqMP OCM

2023-01-09T10:13:58+00:00

Add EDAC support for Xilinx ZynqMP OCM Controller, so this driver reports CE and UE errors upon interrupt generation. Also add debugfs files for error injection. On Xilinx ZynqMP platform, both OCM Controller driver(zynqmp_edac) and DDR Memory Controller driver(synopsys_edac) co-exist which means both can be loaded at a time. This scenario is tested on Xilinx ZynqMP platform. Fix following issue reported by the robot: "MAINTAINERS references a file that doesn't exist: Documentation/devicetree/bindings/edac/xlnx,zynqmp-ocmc.yaml" [ bp: - Massage commit message - s/EDAC_ZYNQMP_OCM/EDAC_ZYNQMP/ - Touchups ] Reported-by: kernel test robot Co-developed-by: Shubhrajyoti Datta Signed-off-by: Shubhrajyoti Datta Signed-off-by: Sai Krishna Potthuri Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/r/20230104084512.1855243-3-sai.krishna.potthuri@amd.com

Merge branches 'edac-ghes' and 'edac-misc' into edac-updates-for-v6.2

2022-12-12T14:40:03+00:00

Combine all queued EDAC changes for submission into v6.2: * ras/edac-ghes: EDAC/igen6: Return the correct error type when not the MC owner apei/ghes: Use xchg_release() for updating new cache slot instead of cmpxchg() EDAC: Check for GHES preference in the chipset-specific EDAC drivers EDAC/ghes: Make ghes_edac a proper module EDAC/ghes: Prepare to make ghes_edac a proper module EDAC/ghes: Add a notifier for reporting memory errors efi/cper: Export several helpers for ghes_edac to use * ras/edac-misc: EDAC/i10nm: fix refcount leak in pci_get_dev_wrapper() EDAC/i5400: Fix typo in comment: vaious -> various EDAC/mc_sysfs: Increase legacy channel support to 12 MAINTAINERS: Make Mauro EDAC reviewer MAINTAINERS: Make Manivannan Sadhasivam the maintainer of qcom_edac EDAC/i5000: Mark as BROKEN Signed-off-by: Borislav Petkov (AMD)

EDAC/ghes: Make ghes_edac a proper module

2022-10-21T19:59:19+00:00

Commit dc4e8c07e9e2 ("ACPI: APEI: explicit init of HEST and GHES in apci_init()") introduced a bug leading to ghes_edac_register() to be invoked before edac_init(). Because at that time the bus "edac" hadn't been even registered, this created sysfs nodes as /devices/mc0 instead of /sys/devices/system/edac/mc/mc0 on an Ampere eMag server. Fix this by turning ghes_edac into a proper module. The list of GHES devices returned is not protected from being modified concurrently but it is pretty static as it gets created only during GHES init and latter is not a module so... [ bp: Massage. ] Fixes: dc4e8c07e9e2 ("ACPI: APEI: explicit init of HEST and GHES in apci_init()") Co-developed-by: Borislav Petkov Signed-off-by: Borislav Petkov Signed-off-by: Jia He Signed-off-by: Borislav Petkov Link: https://lore.kernel.org/r/20221010023559.69655-5-justin.he@arm.com

EDAC/i5000: Mark as BROKEN

2022-10-17T14:39:32+00:00

i5000_edac supports very old hardware which isn't available and it's been broken for single/dual channel for many years without anyone noticing. Marking as BROKEN. Signed-off-by: Aristeu Rozanski Signed-off-by: Borislav Petkov Link: https://lore.kernel.org/r/20220921181009.oxytvicy6sry6it7@redhat.com

soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.

2022-10-13T18:06:51+00:00

Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu Signed-off-by: Zong Li Co-developed-by: Zong Li Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt

EDAC, pnd2: convert to use common P2SB accessor

2022-07-14T09:50:36+00:00

Since we have a common P2SB accessor in tree we may use it instead of open coded variants. Replace custom code by p2sb_bar() call. Signed-off-by: Andy Shevchenko Tested-by: Henning Schild Reviewed-by: Tony Luck Signed-off-by: Lee Jones

EDAC/synopsys: Add driver support for i.MX platforms

2022-04-28T13:15:59+00:00

i.MX8MP use Synopsys v3.70a DDR controller IP so add support for it with the Synopsys driver. Signed-off-by: Sherry Sun Signed-off-by: Borislav Petkov Acked-by: Michal Simek Link: https://lore.kernel.org/r/20220428023209.18087-1-sherry.sun@nxp.com

EDAC/ghes: Unify CPER memory error location reporting

2022-04-08T09:31:18+00:00

Switch the GHES EDAC memory error reporting functions to use the common CPER ones and get rid of code duplication. [ bp: - rewrite commit message, remove useless text - rip out useless reformatting - align function params on the opening brace - rename function to a more descriptive name - drop useless function exports - handle buffer lengths properly when printing other detail - remove useless casting ] Signed-off-by: Shuai Xue Signed-off-by: Borislav Petkov Link: https://lore.kernel.org/r/20220308144053.49090-3-xueshuai@linux.alibaba.com

EDAC/synopsys: Enable the driver on Intel's N5X platform

2021-11-20T18:41:48+00:00

Intel's N5X platform is also using the Synopsys EDAC controller. Signed-off-by: Dinh Nguyen Signed-off-by: Borislav Petkov Acked-by: Michal Simek Link: https://lkml.kernel.org/r/20211012190709.1504152-3-dinguyen@kernel.org