<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/edac/Kconfig, branch v6.1.168</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.1.168</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.1.168'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2022-10-13T18:06:51+00:00</updated>
<entry>
<title>soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.</title>
<updated>2022-10-13T18:06:51+00:00</updated>
<author>
<name>Greentime Hu</name>
<email>greentime.hu@sifive.com</email>
</author>
<published>2022-09-13T06:18:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ca120a79cf5a3323172c82e77efd70ae10d120ef'/>
<id>urn:sha1:ca120a79cf5a3323172c82e77efd70ae10d120ef</id>
<content type='text'>
Since composable cache may be L3 cache if there is a L2 cache, we should
use its original name composable cache to prevent confusion.

There are some new lines were generated due to adding the compatible
"sifive,ccache0" into ID table and indent requirement.

The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to
apply the change as well.

Signed-off-by: Greentime Hu &lt;greentime.hu@sifive.com&gt;
Signed-off-by: Zong Li &lt;zong.li@sifive.com&gt;
Co-developed-by: Zong Li &lt;zong.li@sifive.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt &lt;palmer@rivosinc.com&gt;
</content>
</entry>
<entry>
<title>EDAC, pnd2: convert to use common P2SB accessor</title>
<updated>2022-07-14T09:50:36+00:00</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2022-06-06T16:41:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=7b2db7049bb9e55efb7e0c8a7169d5a021b50284'/>
<id>urn:sha1:7b2db7049bb9e55efb7e0c8a7169d5a021b50284</id>
<content type='text'>
Since we have a common P2SB accessor in tree we may use it instead of
open coded variants.

Replace custom code by p2sb_bar() call.

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Tested-by: Henning Schild &lt;henning.schild@siemens.com&gt;
Reviewed-by: Tony Luck &lt;tony.luck@intel.com&gt;
Signed-off-by: Lee Jones &lt;lee@kernel.org&gt;
</content>
</entry>
<entry>
<title>EDAC/synopsys: Add driver support for i.MX platforms</title>
<updated>2022-04-28T13:15:59+00:00</updated>
<author>
<name>Sherry Sun</name>
<email>sherry.sun@nxp.com</email>
</author>
<published>2022-04-28T02:32:09+00:00</published>
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<id>urn:sha1:5297ecfe2465951682f888b5f4c2efebe23d011a</id>
<content type='text'>
i.MX8MP use Synopsys v3.70a DDR controller IP so add support for it with
the Synopsys driver.

Signed-off-by: Sherry Sun &lt;sherry.sun@nxp.com&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Acked-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/20220428023209.18087-1-sherry.sun@nxp.com
</content>
</entry>
<entry>
<title>EDAC/ghes: Unify CPER memory error location reporting</title>
<updated>2022-04-08T09:31:18+00:00</updated>
<author>
<name>Shuai Xue</name>
<email>xueshuai@linux.alibaba.com</email>
</author>
<published>2022-03-08T14:40:52+00:00</published>
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<id>urn:sha1:ed27b5df3877458eb24615fd9c202178660db009</id>
<content type='text'>
Switch the GHES EDAC memory error reporting functions to use the common
CPER ones and get rid of code duplication.

  [ bp:
      - rewrite commit message, remove useless text
      - rip out useless reformatting
      - align function params on the opening brace
      - rename function to a more descriptive name
      - drop useless function exports
      - handle buffer lengths properly when printing other detail
      - remove useless casting
  ]

Signed-off-by: Shuai Xue &lt;xueshuai@linux.alibaba.com&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Link: https://lore.kernel.org/r/20220308144053.49090-3-xueshuai@linux.alibaba.com
</content>
</entry>
<entry>
<title>EDAC/synopsys: Enable the driver on Intel's N5X platform</title>
<updated>2021-11-20T18:41:48+00:00</updated>
<author>
<name>Dinh Nguyen</name>
<email>dinguyen@kernel.org</email>
</author>
<published>2021-10-12T19:07:08+00:00</published>
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<id>urn:sha1:f6bc0d8bc2c5872e94e6d51472bd16fc4479622b</id>
<content type='text'>
Intel's N5X platform is also using the Synopsys EDAC controller.

Signed-off-by: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Acked-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Link: https://lkml.kernel.org/r/20211012190709.1504152-3-dinguyen@kernel.org
</content>
</entry>
<entry>
<title>EDAC/igen6: fix core dependency AGAIN</title>
<updated>2021-07-15T18:59:59+00:00</updated>
<author>
<name>Randy Dunlap</name>
<email>rdunlap@infradead.org</email>
</author>
<published>2021-07-15T18:55:31+00:00</published>
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<id>urn:sha1:a1c9ca5f65c9acfd7c02474b9d5cacbd7ea288df</id>
<content type='text'>
My previous patch had a typo/thinko which prevents this driver
from being enabled: change X64_64 to X86_64.

Fixes: 0a9ece9ba154 ("EDAC/igen6: fix core dependency")
Signed-off-by: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Cc: Qiuxu Zhuo &lt;qiuxu.zhuo@intel.com&gt;
Cc: Borislav Petkov &lt;bp@alien8.de&gt;
Cc: Mauro Carvalho Chehab &lt;mchehab@kernel.org&gt;
Cc: linux-edac@vger.kernel.org
Cc: bowsingbetee &lt;bowsingbetee@protonmail.com&gt;
Cc: stable@vger.kernel.org
Signed-off-by: Tony Luck &lt;tony.luck@intel.com&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
</entry>
<entry>
<title>EDAC/igen6: fix core dependency</title>
<updated>2021-06-20T21:04:48+00:00</updated>
<author>
<name>Randy Dunlap</name>
<email>rdunlap@infradead.org</email>
</author>
<published>2021-06-19T16:02:03+00:00</published>
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<id>urn:sha1:0a9ece9ba154dd6205709108180952c55e630833</id>
<content type='text'>
igen6_edac needs mce_register()/unregister() functions,
so it should depend on X86_MCE (or X86_MCE_INTEL).

That change prevents these build errors:

ld: drivers/edac/igen6_edac.o: in function `igen6_remove':
igen6_edac.c:(.text+0x494): undefined reference to `mce_unregister_decode_chain'
ld: drivers/edac/igen6_edac.o: in function `igen6_probe':
igen6_edac.c:(.text+0xf5b): undefined reference to `mce_register_decode_chain'

Fixes: 10590a9d4f23e ("EDAC/igen6: Add EDAC driver for Intel client SoCs using IBECC")
Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Signed-off-by: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Signed-off-by: Tony Luck &lt;tony.luck@intel.com&gt;
Link: https://lore.kernel.org/r/20210619160203.2026-1-rdunlap@infradead.org
</content>
</entry>
<entry>
<title>EDAC: altera: merge ARCH_SOCFPGA and ARCH_STRATIX10</title>
<updated>2021-03-23T16:03:35+00:00</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzysztof.kozlowski@canonical.com</email>
</author>
<published>2021-03-11T15:25:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=098da961d8b8c279d34a8f7cd26ff0317f718df6'/>
<id>urn:sha1:098da961d8b8c279d34a8f7cd26ff0317f718df6</id>
<content type='text'>
Simplify 32-bit and 64-bit Intel SoCFPGA Kconfig options by having only
one for both of them.  This the common practice for other platforms.
Additionally, the ARCH_SOCFPGA is too generic as SoCFPGA designs come
from multiple vendors.

Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@canonical.com&gt;
Signed-off-by: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
</content>
</entry>
<entry>
<title>EDAC/amd64: Limit error injection functionality to supported hw</title>
<updated>2020-12-28T18:36:37+00:00</updated>
<author>
<name>Borislav Petkov</name>
<email>bp@suse.de</email>
</author>
<published>2020-12-22T17:55:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=1865bc71a869ede69098b1f3e65857b4330f0607'/>
<id>urn:sha1:1865bc71a869ede69098b1f3e65857b4330f0607</id>
<content type='text'>
Families up to and including 0x16 allow access to the injection
hardware. Starting with family 0x17, access to those registers is
blocked by security policy.

Limit that only on the families which support it.

Suggested-by: Yazen Ghannam &lt;yazen.ghannam@amd.com&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Link: https://lkml.kernel.org/r/20201222180013.GD13463@zn.tnic
</content>
</entry>
<entry>
<title>EDAC/amd64: Merge error injection sysfs facilities</title>
<updated>2020-12-28T18:36:25+00:00</updated>
<author>
<name>Borislav Petkov</name>
<email>bp@suse.de</email>
</author>
<published>2020-12-15T08:18:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=61810096de3c3ec977c71dbb7e00447d70045163'/>
<id>urn:sha1:61810096de3c3ec977c71dbb7e00447d70045163</id>
<content type='text'>
Merge them into the main driver and put them inside an EDAC_DEBUG
ifdeffery to simplify the driver and have all debugging/injection stuff
behind a debug build-time switch.

No functional changes.

Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Reviewed-by: Yazen Ghannam &lt;yazen.ghannam@amd.com&gt;
Link: https://lkml.kernel.org/r/20201215110517.5215-2-bp@alien8.de
</content>
</entry>
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