kernel/linux.git/drivers/dma, branch master

Merge tag 'dmaengine-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine

2026-04-17T17:29:01+00:00

Pull dmaengine updates from Vinod Koul: "Core: - New devm_of_dma_controller_register() API New Support: - Support for RZ/G3L SoC - Loongson Multi-Channel DMA controller support - Conversion of Xilinx AXI DMA binding - DW AXI CV1800B DMA support - Switchtec DMA engine driver Updates: - AMD MDB Endpoint and non-LL mode support - DW edma virtual IRQ for interrupt-emulation, cyclic transfers support" * tag 'dmaengine-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (65 commits) dmaengine: dw-edma: Add non-LL mode dmaengine: dw-edma: Add AMD MDB Endpoint Support dt-bindings: dmaengine: Fix spelling mistake "Looongson" -> "Looogson" dmaengine: loongson: Fix spelling mistake "Looongson" -> "Looogson" dmaengine: loongson: New driver for the Loongson Multi-Channel DMA controller dt-bindings: dmaengine: Add Loongson Multi-Channel DMA controller dmaengine: loongson: loongson2-apb: Simplify locking with guard() and scoped_guard() dmaengine: loongson: loongson2-apb: Convert to devm_clk_get_enabled() dmaengine: loongson: loongson2-apb: Convert to dmaenginem_async_device_register() dmaengine: loongson: New directory for Loongson DMA controllers drivers dt-bindings: dma: xlnx,axi-dma: Convert to DT schema dt-bindings: dma: rz-dmac: Add conditional schema for RZ/G3L dmaengine: sh: rz-dmac: Add device_{pause,resume}() callbacks dmaengine: sh: rz-dmac: Add device_tx_status() callback dmaengine: sh: rz-dmac: Use rz_lmdesc_setup() to invalidate descriptors dmaengine: sh: rz-dmac: Drop unnecessary local_irq_save() call dmaengine: sh: rz-dmac: Drop goto instruction and label dmaengine: sh: rz-dmac: Drop read of CHCTRL register dmaengine: sh: rz_dmac: add RZ/{T2H,N2H} support dt-bindings: dma: renesas,rz-dmac: document RZ/{T2H,N2H} ...

dmaengine: dw-edma: Add non-LL mode

2026-03-18T09:41:40+00:00

AMD MDB IP supports Linked List (LL) mode as well as non-LL mode. The current code does not have the mechanisms to enable the DMA transactions using the non-LL mode. The following two cases are added with this patch: - For the AMD (Xilinx) only, when a valid physical base address of the device side DDR is not configured, then the IP can still be used in non-LL mode. For all the channels DMA transactions will be using the non-LL mode only. This, the default non-LL mode, is not applicable for Synopsys IP with the current code addition. - If the default mode is LL-mode, for both AMD (Xilinx) and Synosys, and if user wants to use non-LL mode then user can do so via configuring the peripheral_config param of dma_slave_config. Signed-off-by: Devendra K Verma Reviewed-by: Frank Li Link: https://patch.msgid.link/20260318070403.1634706-3-devendra.verma@amd.com Signed-off-by: Vinod Koul

dmaengine: dw-edma: Add AMD MDB Endpoint Support

2026-03-18T09:41:40+00:00

AMD MDB PCIe endpoint support. For AMD specific support added the following - AMD supported PCIe Device IDs and Vendor ID (Xilinx). - AMD MDB specific driver data - AMD MDB specific VSEC capability to retrieve the device DDR base address. Signed-off-by: Devendra K Verma Reviewed-by: Frank Li Link: https://patch.msgid.link/20260318070403.1634706-2-devendra.verma@amd.com Signed-off-by: Vinod Koul

dmaengine: loongson: Fix spelling mistake "Looongson" -> "Looogson"

2026-03-18T09:40:55+00:00

There are a couple of spelling mistakes, one in a comment block and one in a module description. Fix them. Signed-off-by: Colin Ian King Link: https://patch.msgid.link/20260317204631.120332-1-colin.i.king@gmail.com Signed-off-by: Vinod Koul

dmaengine: loongson: New driver for the Loongson Multi-Channel DMA controller

2026-03-17T11:18:55+00:00

This DMA controller appears in Loongson-2K0300 and Loongson-2K3000. It is a chain multi-channel controller that enables data transfers from memory to memory, device to memory, and memory to device, as well as channel prioritization configurable through the channel configuration registers. In addition, there are slight differences between Loongson-2K0300 and Loongson-2K3000, such as channel register offsets and the number of channels. Reviewed-by: Frank Li Signed-off-by: Binbin Zhou Reviewed-by: Huacai Chen Link: https://patch.msgid.link/73bc32ba6249f1eef94fec9b349bc9efa98278ea.1772853681.git.zhoubinbin@loongson.cn Signed-off-by: Vinod Koul

dmaengine: loongson: loongson2-apb: Simplify locking with guard() and scoped_guard()

2026-03-17T11:18:55+00:00

Use guard() and scoped_guard() infrastructure instead of explicitly acquiring and releasing spinlocks to simplify the code and ensure that all locks are released properly. Reviewed-by: Frank Li Signed-off-by: Binbin Zhou Reviewed-by: Huacai Chen Link: https://patch.msgid.link/fb59bb25e5c4fcb84d9aa7b351285fa8d02ea8cb.1772853681.git.zhoubinbin@loongson.cn Signed-off-by: Vinod Koul

dmaengine: loongson: loongson2-apb: Convert to devm_clk_get_enabled()

2026-03-17T11:18:55+00:00

Use the devm_clk_get_enabled() helper function to simplify the probe routine. Reviewed-by: Frank Li Signed-off-by: Binbin Zhou Reviewed-by: Huacai Chen Link: https://patch.msgid.link/4f3aad22d14e730cc040ece8b0ced37853d52876.1772853681.git.zhoubinbin@loongson.cn Signed-off-by: Vinod Koul

dmaengine: loongson: loongson2-apb: Convert to dmaenginem_async_device_register()

2026-03-17T11:18:55+00:00

Use the dmaenginem_async_device_register() helper function to simplify the probe routine. Reviewed-by: Frank Li Signed-off-by: Binbin Zhou Reviewed-by: Huacai Chen Link: https://patch.msgid.link/c56e67ecde38e9a3bda5f88ea3fc20b97a5cba6c.1772853681.git.zhoubinbin@loongson.cn Signed-off-by: Vinod Koul

dmaengine: loongson: New directory for Loongson DMA controllers drivers

2026-03-17T11:18:55+00:00

Gather the Loongson DMA controllers under drivers/dma/loongson/ Reviewed-by: Frank Li Signed-off-by: Binbin Zhou Reviewed-by: Keguang Zhang Reviewed-by: Huacai Chen Link: https://patch.msgid.link/0a0853a85630724741061f6fe08680610e49a06e.1772853681.git.zhoubinbin@loongson.cn Signed-off-by: Vinod Koul

dmaengine: xilinx_dma: Fix reset related timeout with two-channel AXIDMA

2026-03-17T11:03:32+00:00

A single AXIDMA controller can have one or two channels. When it has two channels, the reset for both are tied together: resetting one channel resets the other as well. This creates a problem where resetting one channel will reset the registers for both channels, including clearing interrupt enable bits for the other channel, which can then lead to timeouts as the driver is waiting for an interrupt which never comes. The driver currently has a probe-time work around for this: when a channel is created, the driver also resets and enables the interrupts. With two channels the reset for the second channel will clear the interrupt enables for the first one. The work around in the driver is just to manually enable the interrupts again in xilinx_dma_alloc_chan_resources(). This workaround only addresses the probe-time issue. When channels are reset at runtime (e.g., in xilinx_dma_terminate_all() or during error recovery), there's no corresponding mechanism to restore the other channel's interrupt enables. This leads to one channel having its interrupts disabled while the driver expects them to work, causing timeouts and DMA failures. A proper fix is a complicated matter, as we should not reset the other channel when it's operating normally. So, perhaps, there should be some kind of synchronization for a common reset, which is not trivial to implement. To add to the complexity, the driver also supports other DMA types, like VDMA, CDMA and MCDMA, which don't have a shared reset. However, when the two-channel AXIDMA is used in the (assumably) normal use case, providing DMA for a single memory-to-memory device, the common reset is a bit smaller issue: when something bad happens on one channel, or when one channel is terminated, the assumption is that we also want to terminate the other channel. And thus resetting both at the same time is "ok". With that line of thinking we can implement a bit better work around than just the current probe time work around: let's enable the AXIDMA interrupts at xilinx_dma_start_transfer() instead. This ensures interrupts are enabled whenever a transfer starts, regardless of any prior resets that may have cleared them. This approach is also more logical: enable interrupts only when needed for a transfer, rather than at resource allocation time, and, I think, all the other DMA types should also use this model, but I'm reluctant to do such changes as I cannot test them. The reset function still enables interrupts even though it's not needed for AXIDMA anymore, but it's common code for all DMA types (VDMA, CDMA, MCDMA), so leave it unchanged to avoid affecting other variants. Signed-off-by: Tomi Valkeinen Fixes: c0bba3a99f07 ("dmaengine: vdma: Add Support for Xilinx AXI Direct Memory Access Engine") Link: https://patch.msgid.link/20260311-xilinx-dma-fix-v2-1-a725abb66e3c@ideasonboard.com Signed-off-by: Vinod Koul