kernel/linux.git/drivers/dma/xilinx, branch v5.9.12

dmaengine: xilinx_dma: use readl_poll_timeout_atomic variant

2020-12-02T07:51:49+00:00

[ Upstream commit 0ba2df09f1500d3f27398a3382b86d39c3e6abe2 ] The xilinx_dma_poll_timeout macro is sometimes called while holding a spinlock (see xilinx_dma_issue_pending() for an example) this means we shouldn't sleep when polling the dma channel registers. To address it in xilinx poll timeout macro use readl_poll_timeout_atomic instead of readl_poll_timeout variant. Signed-off-by: Marc Ferland Signed-off-by: Radhey Shyam Pandey Link: https://lore.kernel.org/r/1604473206-32573-2-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin

dmaengine: xilinx_dma: Fix SG capability check for MCDMA

2020-11-24T12:38:58+00:00

[ Upstream commit 96d5d884f78306206d745d856aad322becd100c3 ] The SG capability is inherently present with Multichannel DMA operation. The register used to check for this capability with other DMA driver types is not defined for MCDMA. Fixes: 6ccd692bfb7f ("dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support") Signed-off-by: Matthew Murrian Signed-off-by: Radhey Shyam Pandey Link: https://lore.kernel.org/r/1604473206-32573-4-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin

dmaengine: xilinx_dma: Fix usage of xilinx_aximcdma_tx_segment

2020-11-24T12:38:57+00:00

[ Upstream commit c8ae7932997d0cc92d016829138074c7520248e5 ] Several code sections incorrectly use struct xilinx_axidma_tx_segment instead of struct xilinx_aximcdma_tx_segment when operating as Multichannel DMA. As their structures are similar, this just works. Fixes: 6ccd692bfb7f ("dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support") Signed-off-by: Matthew Murrian Signed-off-by: Radhey Shyam Pandey Link: https://lore.kernel.org/r/1604473206-32573-3-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin

dmaengine: xilinx: dpdma: Fix kerneldoc warning

2020-07-22T16:31:13+00:00

Document the struct xilinx_dpdma_chan desc field to fix a kerneldoc undocumented member warning (which can be reproduced by compiling with W=1). Signed-off-by: Laurent Pinchart Link: https://lore.kernel.org/r/20200722161747.30048-1-laurent.pinchart@ideasonboard.com Signed-off-by: Vinod Koul

dmaengine: xilinx: dpdma: add missing kernel doc

2020-07-22T16:30:51+00:00

xilinx_dpdma_sw_desc_set_dma_addrs() documentation is missing describing 'xdev', so add it drivers/dma/xilinx/xilinx_dpdma.c:313: warning: Function parameter or member 'xdev' not described in 'xilinx_dpdma_sw_desc_set_dma_addrs' Link: https://lore.kernel.org/r/20200718135201.191881-2-vkoul@kernel.org Reviewed-by: Laurent Pinchart Signed-off-by: Vinod Koul

dmaengine: xilinx: dpdma: remove comparison of unsigned expression

2020-07-22T16:30:19+00:00

xilinx_dpdma_config() channel id is unsigned int and compares with ZYNQMP_DPDMA_VIDEO0 which is zero, so remove this comparison drivers/dma/xilinx/xilinx_dpdma.c:1073:15: warning: comparison of unsigned expression in ‘>= 0’ is always true [-Wtype-limits] if (chan->id >= ZYNQMP_DPDMA_VIDEO0 && chan->id <= ZYNQMP_DPDMA_VIDEO2) Link: https://lore.kernel.org/r/20200718135201.191881-1-vkoul@kernel.org Reviewed-by: Laurent Pinchart Signed-off-by: Vinod Koul

dmaengine: xilinx: dpdma: Add the Xilinx DisplayPort DMA engine driver

2020-07-17T06:07:59+00:00

The ZynqMP DisplayPort subsystem includes a DMA engine called DPDMA with 6 DMa channels (4 for display and 2 for audio). This driver exposes the DPDMA through the dmaengine API, to be used by audio (ALSA) and display (DRM) drivers for the DisplayPort subsystem. Signed-off-by: Hyun Kwon Signed-off-by: Tejas Upadhyay Signed-off-by: Michal Simek Signed-off-by: Laurent Pinchart Link: https://lore.kernel.org/r/20200717013337.24122-4-laurent.pinchart@ideasonboard.com Signed-off-by: Vinod Koul

dmaengine: zynqmp_dma: Move list_del inside zynqmp_dma_free_descriptor.

2020-05-15T05:51:11+00:00

List elements are not formally removed from list during zynqmp_dma_reset. Signed-off-by: Rafal Hibner Link: https://lore.kernel.org/r/20200506102844.2259-1-rafal.hibner@secom.com.pl Signed-off-by: Vinod Koul

dmaengine: xilinx_dma: Add missing check for empty list

2020-04-15T16:12:11+00:00

The DMA transfer might finish just after checking the state with dma_cookie_status, but before the lock is acquired. Not checking for an empty list in xilinx_dma_tx_status may result in reading random data or data corruption when desc is written to. This can be reliably triggered by using dma_sync_wait to wait for DMA completion. Signed-off-by: Sebastian von Ohr Tested-by: Radhey Shyam Pandey Link: https://lore.kernel.org/r/20200303130518.333-1-vonohr@smaract.com Signed-off-by: Vinod Koul

dmaengine: xilinx_dma: In dma channel probe fix node order dependency

2020-02-25T05:47:54+00:00

In overlay application we noticed that dma channel node probe order is inverted i.e s2mm channel is probed first followed by mm2s channel. The reason for this inversion is fdtoverlay utility which uses a function called fdt_add_subnode(*). It stores the subnodes after the properties, this has the effect of inserting the new subnode before any others and the end result is a reversal. Because of this inverted channel probe order, the node probed first is assigned a '0' index instead of Channel ID should be '0' for tx and '1' for rx and dmatest client using the DT convention fails in dma transfer as channel are swapped. To fix above behavior and make channel assignment index independent of probe order, always assign mm2s channel at '0' index and the s2mm channel at IP specific fixed offset derived from the max_channels count. Signed-off-by: Radhey Shyam Pandey Link: https://lore.kernel.org/r/1580388865-9960-3-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul