kernel/linux.git/drivers/dma/xilinx, branch v4.11.5

dmengine: xilinx_dma: convert callback to helper function

2016-08-08T02:41:43+00:00

Move the xilinx driver to new dmaengine callback Signed-off-by: Vinod Koul

dmaengine: zynqmp_dma: add missing MODULE_LICENSE

2016-07-24T06:25:17+00:00

We get a warning about the missing MODULE_LICENSE tag for this newly added driver module: WARNING: modpost: missing MODULE_LICENSE() in drivers/dma/xilinx/zynqmp_dma.o see include/linux/module.h for more information This adds a "GPL" license, matching the "version 2 or later" information in the comment at the start of the file. Signed-off-by: Arnd Bergmann Acked-by: Kedareswara rao Appana Signed-off-by: Vinod Koul

dmaengine: zynqmp_dma: Fix static checker warning

2016-07-24T05:49:22+00:00

This patch fixes the below static checker warning drivers/dma/xilinx/zynqmp_dma.c:973 zynqmp_dma_chan_probe() warn: was && intended here instead of ||? Reported-by: Dan Carpenter Signed-off-by: Kedareswara rao Appana Signed-off-by: Vinod Koul

dmaengine: zynqmp: avoid cast warning

2016-07-12T04:33:16+00:00

The newly added zynqmp_dma driver produces a warning on 32-bit architectures when dma_addr_t is 64-bit wide: drivers/dma/xilinx/zynqmp_dma.c: In function 'zynqmp_dma_config_sg_ll_desc': drivers/dma/xilinx/zynqmp_dma.c:321:9: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] ((dma_addr_t)sdesc - (dma_addr_t)chan->desc_pool_v); ^ drivers/dma/xilinx/zynqmp_dma.c:321:29: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] ((dma_addr_t)sdesc - (dma_addr_t)chan->desc_pool_v); This changes the cast to the more appropriate uintptr_t. Signed-off-by: Arnd Bergmann Signed-off-by: Vinod Koul

dmaengine: xilinx: Fix race condition in axi dma cyclic dma mode

2016-07-12T04:31:36+00:00

In cyclic DMA mode need to link the tail bd segment with the head bd segment to process bd's in cyclic. Current driver is doing this only for tx channel needs to update the same for rx channel case also. This patch fixes the same. Signed-off-by: Kedareswara rao Appana Signed-off-by: Vinod Koul

dmaengine: Add Xilinx zynqmp dma engine driver support

2016-07-08T05:55:34+00:00

Added the driver for zynqmp dma engine used in Zynq UltraScale+ MPSoC. This dma controller supports memory to memory and I/O to I/O buffer transfers. Signed-off-by: Kedareswara rao Appana Signed-off-by: Vinod Koul

dmaengine: xilinx: Use different channel names for each dma

2016-07-08T05:21:49+00:00

Current driver assumes that child node channel name is either "xlnx,axi-vdma-mm2s-channel" or "xlnx,axi-vdma-s2mm-channel" which is confusing the users of AXI DMA and CDMA. This patch fixes this issue by using different channel names for the AXI DMA and AXI CDMA child nodes. Signed-off-by: Kedareswara rao Appana Acked-by: Rob Herring Signed-off-by: Vinod Koul

dmaengine: xilinx: Rename driver and config

2016-07-08T05:21:35+00:00

In the existing vdma driver support for AXI DMA and CDMA got added so the driver is no longer VDMA specific. This patch renames the driver and DT binding doc to xilinx_dma and updates the Kconfig description for all the DMAS. Signed-off-by: Kedareswara rao Appana Signed-off-by: Vinod Koul

dmaengine: vdma: Add support for mulit-channel dma mode

2016-07-08T05:20:38+00:00

This patch adds support for AXI DMA multi-channel dma mode Multichannel mode enables DMA to connect to multiple masters and slaves on the streaming side. In Multichannel mode AXI DMA supports 2D transfers. Signed-off-by: Kedareswara rao Appana Signed-off-by: Vinod Koul

dmaengine: vdma: Add 64 bit addressing support for the axi cdma

2016-06-21T05:35:23+00:00

The AXI CDMA is a soft ip, which can be programmed to support 32 bit addressing or greater than 32 bit addressing. When the AXI CDMA ip is configured for 32 bit address space in simple dma mode the source/destination buffer address is specified by a single register(18h for Source buffer address and 20h for Destination buffer address). When configured in SG mode the current descriptor and tail descriptor are specified by a Single register(08h for curdesc 10h for tail desc). When the AXI CDMA core is configured for an address space greater than 32 then each buffer address or descriptor address is specified by a combination of two registers. The first register specifies the LSB 32 bits of address, while the next register specifies the MSB 32 bits of address. For example, 08h will specify the LSB 32 bits while 0Ch will specify the MSB 32 bits of the first start address. So we need to program two registers at a time. This patch adds the 64 bit addressing support to the axicdma IP in the driver. Signed-off-by: Kedareswara rao Appana Signed-off-by: Vinod Koul