kernel/linux.git/drivers/cxl, branch master

Merge tag 'cxl-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl

2026-04-17T22:52:58+00:00

Pull CXL (Compute Express Link) updates from Dave Jiang: "The significant change of interest is the handling of soft reserved memory conflict between CXL and HMEM. In essence CXL will be the first to claim the soft reserved memory ranges that belongs to CXL and attempt to enumerate them with best effort. If CXL is not able to enumerate the ranges it will punt them to HMEM. There are also MAINTAINERS email changes from Dan Williams and Jonathan Cameron" * tag 'cxl-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl: (37 commits) MAINTAINERS: Update Jonathan Cameron's email address cxl/hdm: Add support for 32 switch decoders MAINTAINERS: Update address for Dan Williams tools/testing/cxl: Enable replay of user regions as auto regions cxl/region: Add a region sysfs interface for region lock status tools/testing/cxl: Test dax_hmem takeover of CXL regions tools/testing/cxl: Simulate auto-assembly failure dax/hmem: Parent dax_hmem devices dax/hmem: Fix singleton confusion between dax_hmem_work and hmem devices dax/hmem: Reduce visibility of dax_cxl coordination symbols cxl/region: Constify cxl_region_resource_contains() cxl/region: Limit visibility of cxl_region_contains_resource() dax/cxl: Fix HMEM dependencies cxl/region: Fix use-after-free from auto assembly failure cxl/core: Check existence of cxl_memdev_state in poison test cxl/core: use cleanup.h for devm_cxl_add_dax_region cxl/core/region: move dax region device logic into region_dax.c cxl/core/region: move pmem region driver logic into region_pmem.c dax/hmem, cxl: Defer and resolve Soft Reserved ownership cxl/region: Add helper to check Soft Reserved containment by CXL regions ...

Merge branch 'for-7.1/cxl-misc' into cxl-for-next

2026-04-10T18:11:53+00:00

cxl/hdm: Add support for 32 switch decoders

2026-04-10T15:32:14+00:00

Per CXL r4.0 section 8.2.4.20.1. CXL host bridge and switch ports can support 32 HDM decoders. Current implementation misses some decoders on CXL host bridge and switch in the case that the value of Decoder Count field in CXL HDM decoder Capability Register is greater than or equal to 9. Update calculation implementation to ensure the decoder count calculation is correct for CXL host bridge/switch ports. Signed-off-by: Li Ming Reviewed-by: Gregory Price Reviewed-by: Dave Jiang Reviewed-by: Alison Schofield Link: https://patch.msgid.link/20260321061459.1910205-1-ming.li@zohomail.com Signed-off-by: Dave Jiang

Merge branch 'for-7.1/cxl-region-refactor' into cxl-for-next

2026-04-03T19:30:57+00:00

Refactor CXL core/region code to make region code more manageable by splitting out DAX and PMEM code from RAM handling code. cxl/core: use cleanup.h for devm_cxl_add_dax_region cxl/core/region: move dax region device logic into region_dax.c cxl/core/region: move pmem region driver logic into region_pmem.c

Merge branch 'for-7.1/dax-hmem' into cxl-for-next

2026-04-03T19:24:18+00:00

The series addresses conflicts between HMEM and CXL when handling Soft Reserved memory ranges. CXL will try best effort in claiming the Soft Reserved memory region that are CXL regions. If fails, it will punt back to HMEM. tools/testing/cxl: Test dax_hmem takeover of CXL regions tools/testing/cxl: Simulate auto-assembly failure dax/hmem: Parent dax_hmem devices dax/hmem: Fix singleton confusion between dax_hmem_work and hmem devices dax/hmem: Reduce visibility of dax_cxl coordination symbols cxl/region: Constify cxl_region_resource_contains() cxl/region: Limit visibility of cxl_region_contains_resource() dax/cxl: Fix HMEM dependencies cxl/region: Fix use-after-free from auto assembly failure dax/hmem, cxl: Defer and resolve Soft Reserved ownership cxl/region: Add helper to check Soft Reserved containment by CXL regions dax: Track all dax_region allocations under a global resource tree dax/cxl, hmem: Initialize hmem early and defer dax_cxl binding dax/hmem: Gate Soft Reserved deferral on DEV_DAX_CXL dax/hmem: Request cxl_acpi and cxl_pci before walking Soft Reserved ranges dax/hmem: Factor HMEM registration into __hmem_register_device() dax/bus: Use dax_region_put() in alloc_dax_region() error path

Merge branch 'for-7.1/cxl-type2-support' into cxl-for-next

2026-04-03T19:18:23+00:00

Prep patches for CXL type2 accelerator basic support cxl/region: Factor out interleave granularity setup cxl/region: Factor out interleave ways setup cxl: Make region type based on endpoint type cxl/pci: Remove redundant cxl_pci_find_port() call cxl: Move pci generic code from cxl_pci to core/cxl_pci cxl: export internal structs for external Type2 drivers cxl: support Type2 when initializing cxl_dev_state

Merge branch 'for-7.1/cxl-consolidate-endpoint' into cxl-for-next

2026-04-03T19:15:11+00:00

Add code to ensure the endpoint has completed initialization before usage. cxl/pci: Check memdev driver binding status in cxl_reset_done() cxl/pci: Hold memdev lock in cxl_event_trace_record()

cxl/region: Add a region sysfs interface for region lock status

2026-04-01T16:59:58+00:00

There are 3 scenarios that leads to a locked region: 1. A region is created on a root decoder with Fixed Device Confiuration attribute. 2. CXL_HDM_DECODER0_CTRL_LOCK. Both 1 & 1 are well described in: commit 2230c4bdc412 ("cxl: Add handling of locked CXL decoder") 3) Platform that has region creation with PRMT address translation always locks the region, regardless of the FIXED attribute or decoder ctrl bit. Region locked means region destroy operations are not permitted. CXL region driver returns -EPERM for region destroy operations. Although the locked status of the corresponding root decoder implies the region is also locked, exposing the region lock status directly to userspace improves usability for users who may not be aware of this relationship. [ dj: Amended commit log with additional locking scenarios. ] Signed-off-by: Li Ming Reviewed-by: Dave Jiang Reviewed-by: Alejandro Lucero Reviewed-by: Alison Schofield Link: https://patch.msgid.link/20260401124951.1290041-1-ming.li@zohomail.com Signed-off-by: Dave Jiang

cxl/region: Constify cxl_region_resource_contains()

2026-04-01T15:12:17+00:00

The call to cxl_region_resource_contains() in hmem_register_cxl_device() need not cast away 'const'. The problem is the usage of the bus_for_each_dev() API which does not mark its @data parameter as 'const'. Switch to bus_find_device() which does take 'const' @data, fixup cxl_region_resource_contains() and its caller. Signed-off-by: Dan Williams Reviewed-by: Ira Weiny Reviewed-by: Alison Schofield Reviewed-by: Dave Jiang Link: https://patch.msgid.link/20260327052821.440749-5-dan.j.williams@intel.com Signed-off-by: Dave Jiang

cxl/region: Limit visibility of cxl_region_contains_resource()

2026-04-01T15:12:17+00:00

The dax_hmem dependency on cxl_region_contains_resource() is a one-off special case. It is not suitable for other use cases. Move the definition to the other CONFIG_CXL_REGION guarded definitions in drivers/cxl/cxl.h and include that by a relative path include. This matches what drivers/dax/cxl.c does for its limited private usage of CXL core symbols. Reduce the symbol export visibility from global to just dax_hmem, to further clarify its applicability. Signed-off-by: Dan Williams Reviewed-by: Ira Weiny Reviewed-by: Alison Schofield Reviewed-by: Dave Jiang Link: https://patch.msgid.link/20260327052821.440749-4-dan.j.williams@intel.com Signed-off-by: Dave Jiang