<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/crypto/hisilicon, branch v6.19.11</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.19.11</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.19.11'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2026-03-04T12:19:45+00:00</updated>
<entry>
<title>crypto: hisilicon/qm - move the barrier before writing to the mailbox register</title>
<updated>2026-03-04T12:19:45+00:00</updated>
<author>
<name>Chenghai Huang</name>
<email>huangchenghai2@huawei.com</email>
</author>
<published>2026-01-17T10:18:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=7b4db0587203de49dc4ebbcdf31478e7d9436f57'/>
<id>urn:sha1:7b4db0587203de49dc4ebbcdf31478e7d9436f57</id>
<content type='text'>
[ Upstream commit ebf35d8f9368816c930f5d70783a72716fab5e19 ]

Before sending the data via the mailbox to the hardware, to ensure
that the data accessed by the hardware is the most up-to-date,
a write barrier should be added before writing to the mailbox register.
The current memory barrier is placed after writing to the register,
the barrier order should be modified to be before writing to the register.

Signed-off-by: Chenghai Huang &lt;huangchenghai2@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/trng - support tfms sharing the device</title>
<updated>2026-02-26T23:00:48+00:00</updated>
<author>
<name>Weili Qian</name>
<email>qianweili@huawei.com</email>
</author>
<published>2026-01-17T07:18:21+00:00</published>
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<id>urn:sha1:ce36469987d6550551669f95c07978da17425165</id>
<content type='text'>
[ Upstream commit 3d3135057ff567d5c09fff4c9ef6391a684e8042 ]

Since the number of devices is limited, and the number
of tfms may exceed the number of devices, to ensure that
tfms can be successfully allocated, support tfms
sharing the same device.

Fixes: e4d9d10ef4be ("crypto: hisilicon/trng - add support for PRNG")
Signed-off-by: Weili Qian &lt;qianweili@huawei.com&gt;
Signed-off-by: Chenghai Huang &lt;huangchenghai2@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/sgl - fix inconsistent map/unmap direction issue</title>
<updated>2026-02-26T23:00:46+00:00</updated>
<author>
<name>Chenghai Huang</name>
<email>huangchenghai2@huawei.com</email>
</author>
<published>2025-12-19T03:36:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e33338a81e1ce667f2865916d7d629fdd4c51ea6'/>
<id>urn:sha1:e33338a81e1ce667f2865916d7d629fdd4c51ea6</id>
<content type='text'>
[ Upstream commit 4154f7d3b1c133b909d20c44ecb8277e8482aa6b ]

Ensure that the direction for dma_map_sg and dma_unmap_sg is
consistent.

Fixes: 2566de3e06a3 ("crypto: hisilicon - Use fine grained DMA mapping direction")
Signed-off-by: Chenghai Huang &lt;huangchenghai2@huawei.com&gt;
Reviewed-by: Zenghui Yu &lt;yuzenghui@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/sec2 - support skcipher/aead fallback for hardware queue unavailable</title>
<updated>2026-02-26T23:00:46+00:00</updated>
<author>
<name>Qi Tao</name>
<email>taoqi10@huawei.com</email>
</author>
<published>2025-12-18T13:44:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=2107f9d57c72560667a36e511c86145e4f60f66b'/>
<id>urn:sha1:2107f9d57c72560667a36e511c86145e4f60f66b</id>
<content type='text'>
[ Upstream commit e7507439628052363500d717caffb5c2241854dc ]

When all hardware queues are busy and no shareable queue,
new processes fail to apply for queues. To avoid affecting
tasks, support fallback mechanism when hardware queues are
unavailable.

Fixes: c16a70c1f253 ("crypto: hisilicon/sec - add new algorithm mode for AEAD")
Signed-off-by: Qi Tao &lt;taoqi10@huawei.com&gt;
Signed-off-by: Chenghai Huang &lt;huangchenghai2@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/hpre - support the hpre algorithm fallback</title>
<updated>2026-02-26T23:00:46+00:00</updated>
<author>
<name>Weili Qian</name>
<email>qianweili@huawei.com</email>
</author>
<published>2025-12-18T13:44:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=cc1cdf592f165c331c9075f8d3037b27c11cd6e0'/>
<id>urn:sha1:cc1cdf592f165c331c9075f8d3037b27c11cd6e0</id>
<content type='text'>
[ Upstream commit 6aff4d977e2d582c5d6ff6afd5646c1a459490fa ]

When all hardware queues are busy and no shareable queue,
new processes fail to apply for queues. To avoid affecting
tasks, support fallback mechanism when hardware queues are
unavailable.

HPRE driver supports DH algorithm, limited to prime numbers up to 4K.
It supports prime numbers larger than 4K via fallback mechanism.

Fixes: 05e7b906aa7c ("crypto: hisilicon/hpre - add 'ECDH' algorithm")
Signed-off-by: Weili Qian &lt;qianweili@huawei.com&gt;
Signed-off-by: Chenghai Huang &lt;huangchenghai2@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon - consolidate qp creation and start in hisi_qm_alloc_qps_node</title>
<updated>2026-02-26T23:00:46+00:00</updated>
<author>
<name>Chenghai Huang</name>
<email>huangchenghai2@huawei.com</email>
</author>
<published>2025-12-18T13:44:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=c3ace3bb8605a15b4018b9036e83a0d0443ee2bd'/>
<id>urn:sha1:c3ace3bb8605a15b4018b9036e83a0d0443ee2bd</id>
<content type='text'>
[ Upstream commit 72f3bbebff15e87171271d643ee2672fb8e92031 ]

Consolidate the creation and start of qp into the function
hisi_qm_alloc_qps_node. This change eliminates the need for
each module to perform these steps in two separate phases
(creation and start).

Signed-off-by: Chenghai Huang &lt;huangchenghai2@huawei.com&gt;
Signed-off-by: Weili Qian &lt;qianweili@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Stable-dep-of: 6aff4d977e2d ("crypto: hisilicon/hpre - support the hpre algorithm fallback")
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/zip - support fallback for zip</title>
<updated>2026-02-26T23:00:46+00:00</updated>
<author>
<name>Chenghai Huang</name>
<email>huangchenghai2@huawei.com</email>
</author>
<published>2025-12-18T13:44:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=8ac94874d3efbadbbd0c9a0f8a1f314c37d191cb'/>
<id>urn:sha1:8ac94874d3efbadbbd0c9a0f8a1f314c37d191cb</id>
<content type='text'>
[ Upstream commit 73398f85a430cfebc2ff06ab836d6d9eb1484c79 ]

When the hardware queue resource busy(no shareable queue)
or memery alloc fail in initialization of acomp_alg, use
soft algorithm to complete the work.

Fixes: 1a9e6f59caee ("crypto: hisilicon/zip - remove zlib and gzip")
Signed-off-by: Chenghai Huang &lt;huangchenghai2@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/qm - centralize the sending locks of each module into qm</title>
<updated>2026-02-26T23:00:46+00:00</updated>
<author>
<name>Chenghai Huang</name>
<email>huangchenghai2@huawei.com</email>
</author>
<published>2025-12-18T13:44:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=5d70c905a0bbd64857eed519bf62f3633ad7d162'/>
<id>urn:sha1:5d70c905a0bbd64857eed519bf62f3633ad7d162</id>
<content type='text'>
[ Upstream commit 8cd9b608ee8dea78cac3f373bd5e3b3de2755d46 ]

When a single queue used by multiple tfms, the protection of shared
resources by individual module driver programs is no longer
sufficient. The hisi_qp_send needs to be ensured by the lock in qp.

Fixes: 5fdb4b345cfb ("crypto: hisilicon - add a lock for the qp send operation")
Signed-off-by: Chenghai Huang &lt;huangchenghai2@huawei.com&gt;
Signed-off-by: Weili Qian &lt;qianweili@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/qm - enhance the configuration of req_type in queue attributes</title>
<updated>2026-02-26T23:00:46+00:00</updated>
<author>
<name>Chenghai Huang</name>
<email>huangchenghai2@huawei.com</email>
</author>
<published>2025-12-18T13:44:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=63223f79858de58d35344fc88a27bf23f0398f30'/>
<id>urn:sha1:63223f79858de58d35344fc88a27bf23f0398f30</id>
<content type='text'>
[ Upstream commit 21452eaa06edb5f6038720e643aed0bbfffad9c3 ]

Originally, when a queue was requested, it could only be configured
with the default algorithm type of 0. Now, when multiple tfms use
the same queue, the queue must be selected based on its attributes
to meet the requirements of tfm tasks. So the algorithm type
attribute of queue need to be distinguished. Just like a queue used
for compression in ZIP cannot be used for decompression tasks.

Fixes: 3f1ec97aacf1 ("crypto: hisilicon/qm - Put device finding logic into QM")
Signed-off-by: Chenghai Huang &lt;huangchenghai2@huawei.com&gt;
Signed-off-by: Weili Qian &lt;qianweili@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/hpre: extend tag field to 64 bits for better performance</title>
<updated>2026-02-26T23:00:45+00:00</updated>
<author>
<name>lizhi</name>
<email>lizhi206@huawei.com</email>
</author>
<published>2025-12-18T13:44:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=78d9e4162a840126f5c5142810983e6ecc646512'/>
<id>urn:sha1:78d9e4162a840126f5c5142810983e6ecc646512</id>
<content type='text'>
[ Upstream commit 3a1984758197f7fd4c557dd98090e8e0cf9f498e ]

This commit expands the tag field in hpre_sqe structure from 16-bit
to 64-bit. The change enables storing request addresses directly
in the tag field, allowing callback functions to access request messages
without the previous indirection mechanism.

By eliminating the need for lookup tables, this modification reduces lock
contention and associated overhead, leading to improved efficiency and
simplified code.

Fixes: c8b4b477079d ("crypto: hisilicon - add HiSilicon HPRE accelerator")
Signed-off-by: lizhi &lt;lizhi206@huawei.com&gt;
Signed-off-by: Weili Qian &lt;qianweili@huawei.com&gt;
Signed-off-by: Chenghai Huang &lt;huangchenghai2@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
</feed>
