kernel/linux.git/drivers/crypto/Makefile, branch v4.11.5

crypto: brcm - Add Broadcom SPU driver

2017-02-11T09:55:20+00:00

Add Broadcom Secure Processing Unit (SPU) crypto driver for SPU hardware crypto offload. The driver supports ablkcipher, ahash, and aead symmetric crypto operations. Signed-off-by: Steve Lin Signed-off-by: Rob Rice Signed-off-by: Herbert Xu

crypto: cavium - Enable CPT options crypto for build

2017-02-11T09:55:17+00:00

Add the CPT options in crypto Kconfig and update the crypto Makefile Update the MAINTAINERS file too. Signed-off-by: George Cherian Reviewed-by: David Daney Signed-off-by: Herbert Xu

crypto: mediatek - Add crypto driver support for some MediaTek chips

2016-12-27T09:51:30+00:00

This adds support for the MediaTek hardware accelerator on mt7623/mt2701/mt8521p SoC. This driver currently implement: - SHA1 and SHA2 family(HMAC) hash algorithms. - AES block cipher in CBC/ECB mode with 128/196/256 bits keys. Signed-off-by: Ryder Lee Signed-off-by: Herbert Xu

crypto: drivers - bring back alphabetical order of Makefile

2016-12-27T09:48:47+00:00

THe major content of drivers/crypto/Makefile is sorted, only recent addition break this sort. This patch bring back this alphabetical sorting. Signed-off-by: Corentin Labbe Signed-off-by: Herbert Xu

crypto: add virtio-crypto driver

2016-12-15T22:13:32+00:00

This patch introduces virtio-crypto driver for Linux Kernel. The virtio crypto device is a virtual cryptography device as well as a kind of virtual hardware accelerator for virtual machines. The encryption anddecryption requests are placed in the data queue and are ultimately handled by thebackend crypto accelerators. The second queue is the control queue used to create or destroy sessions for symmetric algorithms and will control some advanced features in the future. The virtio crypto device provides the following cryptoservices: CIPHER, MAC, HASH, and AEAD. For more information about virtio-crypto device, please see: http://qemu-project.org/Features/VirtioCrypto CC: Michael S. Tsirkin CC: Cornelia Huck CC: Stefan Hajnoczi CC: Herbert Xu CC: Halil Pasic CC: David S. Miller CC: Zeng Xin Signed-off-by: Gonglei Signed-off-by: Michael S. Tsirkin

crypto: Added Chelsio Menu to the Kconfig file

2016-08-19T07:00:37+00:00

Adds the config entry for the Chelsio Crypto Driver, Makefile changes for the same. Signed-off-by: Atul Gupta Signed-off-by: Hariprasad Shenai Signed-off-by: David S. Miller

crypto: mxc-scc - add basic driver for the MXC SCC

2016-04-15T14:36:35+00:00

According to the Freescale GPL driver code, there are two different Security Controller (SCC) versions: SCC and SCC2. The SCC is found on older i.MX SoCs, e.g. the i.MX25. This is the version implemented and tested here. As there is no publicly available documentation for this IP core, all information about this unit is gathered from the GPL'ed driver from Freescale. Signed-off-by: Steffen Trumtrar Signed-off-by: Herbert Xu

crypto: rockchip - add crypto driver for rk3288

2015-11-27T13:19:32+00:00

Crypto driver support: ecb(aes) cbc(aes) ecb(des) cbc(des) ecb(des3_ede) cbc(des3_ede) You can alloc tags above in your case. And other algorithms and platforms will be added later on. Signed-off-by: Zain Wang Tested-by: Heiko Stuebner Signed-off-by: Herbert Xu

crypto: sunxi-ss - Add Allwinner Security System crypto accelerator

2015-07-20T07:54:08+00:00

Add support for the Security System included in Allwinner SoC A20. The Security System is a hardware cryptographic accelerator that support: - MD5 and SHA1 hash algorithms - AES block cipher in CBC/ECB mode with 128/196/256bits keys. - DES and 3DES block cipher in CBC/ECB mode Signed-off-by: LABBE Corentin Signed-off-by: Herbert Xu

crypto: marvell/cesa - add a new driver for Marvell's CESA

2015-06-19T14:18:03+00:00

The existing mv_cesa driver supports some features of the CESA IP but is quite limited, and reworking it to support new features (like involving the TDMA engine to offload the CPU) is almost impossible. This driver has been rewritten from scratch to take those new features into account. This commit introduce the base infrastructure allowing us to add support for DMA optimization. It also includes support for one hash (SHA1) and one cipher (AES) algorithm, and enable those features on the Armada 370 SoC. Other algorithms and platforms will be added later on. Signed-off-by: Boris Brezillon Signed-off-by: Arnaud Ebalard Signed-off-by: Herbert Xu