Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v4.17.1 2018-03-23T15:48:37+00:00 2018-03-23T15:48:37+00:00 Arnd Bergmann arnd@arndb.de 2018-03-14T15:35:32+00:00 urn:sha1:9678a8dc53c129599be45e7172b3a0fe6efa7989 The blackfin architecture is getting removed, so this driver won't be used any more. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> 2018-03-02T16:03:16+00:00 Gilad Ben-Yossef gilad@benyossef.com 2018-02-19T14:51:23+00:00 urn:sha1:27b3b22dd98caef023cbaa4871b356e4596a81af Add support for the legacy CryptoCell 630 and 710 revs. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> 2018-02-15T15:26:40+00:00 Gilad Ben-Yossef gilad@benyossef.com 2018-01-22T09:27:00+00:00 urn:sha1:4c3f97276e156820a0433bf7b59a4df1100829ae Introduce basic low level Arm TrustZone CryptoCell HW support. This first patch doesn't actually register any Crypto API transformations, these will follow up in the next patch. This first revision supports the CC 712 REE component. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> 2018-01-25T14:10:31+00:00 Corentin LABBE clabbe.montjoie@gmail.com 2018-01-17T18:50:56+00:00 urn:sha1:980b4c95e78e4113cb7b9f430f121dab1c814b6c Since CRYPTO_SHA384 does not exists, Kconfig should not select it. Anyway, all SHA384 stuff is in CRYPTO_SHA512 which is already selected. Fixes: a21eb94fc4d3i ("crypto: axis - add ARTPEC-6/7 crypto accelerator driver") Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> 2017-11-03T14:11:25+00:00 Kamil Konieczny k.konieczny@partner.samsung.com 2017-10-25T15:27:35+00:00 urn:sha1:c2afad6c6105783a72a2f7b69834a489120a1a7c Add support for MD5, SHA1, SHA256 hash algorithms for Exynos HW. It uses the crypto framework asynchronous hash api. It is based on omap-sham.c driver. S5P has some HW differencies and is not implemented. Modifications in s5p-sss: - Add hash supporting structures and functions. - Modify irq handler to handle both aes and hash signals. - Resize resource end in probe if EXYNOS_HASH is enabled in Kconfig. - Add new copyright line and new author. - Tested on Odroid-U3 with Exynos 4412 CPU, kernel 4.13-rc6 with crypto run-time self test testmgr and with tcrypt module with: modprobe tcrypt sec=1 mode=N where N=402, 403, 404 (MD5, SHA1, SHA256). Modifications in drivers/crypto/Kconfig: - Add new CRYPTO_DEV_EXYNOS_HASH, depend on !EXYNOS_RNG and CRYPTO_DEV_S5P - Select sw algorithms MD5, SHA1 and SHA256 in EXYNOS_HASH as they are needed for fallback. Acked-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Kamil Konieczny <k.konieczny@partner.samsung.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> 2017-11-03T13:53:30+00:00 Boris BREZILLON boris.brezillon@free-electrons.com 2017-10-11T13:16:19+00:00 urn:sha1:27b43fd95b144484713855c6d4fe832d22e48838 All defconfigs selecting the old driver have been patched to select the new one instead. We can now remove the old driver along with the allhwsupports module parameter in the new driver that was used to check whether the new driver was allowed to take control of the CESA engine or not. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> 2017-10-12T14:55:19+00:00 Christian Lamparter chunkeey@gmail.com 2017-10-03T23:00:15+00:00 urn:sha1:a0aae821ba3d35a49d4d0143dfb0c07eee22130e This patch enhances existing interfaces and functions to support AEAD ciphers in the next patches. Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> 2017-08-22T06:54:52+00:00 Lars Persson lars.persson@axis.com 2017-08-10T12:53:53+00:00 urn:sha1:a21eb94fc4d3c6472de53bd30a543ec06eaf8914 This is an asynchronous crypto API driver for the accelerator present in the ARTPEC-6 and -7 SoCs from Axis Communications AB. The driver supports AES in ECB/CTR/CBC/XTS/GCM modes and SHA1/2 hash standards. Signed-off-by: Lars Persson <larper@axis.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> 2017-07-18T09:51:19+00:00 Brijesh Singh brijesh.singh@amd.com 2017-07-06T14:59:14+00:00 urn:sha1:720419f01832f7e697cb80480b97b2a1e96045cd The CCP device is part of the AMD Secure Processor. In order to expand the usage of the AMD Secure Processor, create a framework that allows functional components of the AMD Secure Processor to be initialized and handled appropriately. Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Acked-by: Gary R Hook <gary.hook@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> 2017-07-18T09:50:58+00:00 Tudor-Dan Ambarus tudor.ambarus@microchip.com 2017-07-05T10:07:59+00:00 urn:sha1:11105693fa05f499532b330da65c78ff93ed4440 Add ECDH support for ATECC508A (I2C) device. The device features hardware acceleration for the NIST standard P256 prime curve and supports the complete key life cycle from private key generation to ECDH key agreement. Random private key generation is supported internally within the device to ensure that the private key can never be known outside of the device. If the user wants to use its own private keys, the driver will fallback to the ecdh software implementation. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>