Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=linux-5.9.y 2020-08-04T10:44:53+00:00 2020-08-04T10:44:53+00:00 Rafael J. Wysocki rafael.j.wysocki@intel.com 2020-08-04T10:44:53+00:00 urn:sha1:9ac1fb156a40b88fddb2e2b8c36e127b0d01fb8e Pull ARM cpufreq driver changes for v5.9-rc1 from Viresh Kumar: "Here are the details: - Adaptive voltage scaling (AVS) support and minor cleanups for brcmstb driver (Florian Fainelli and Markus Mayer). - A new tegra driver and cleanup for the existing one (Sumit Gupta and Jon Hunter). - Bandwidth level support for Qcom driver along with OPP changes (Sibi Sankar). - Cleanups to sti, cpufreq-dt, ap806, CPPC drivers (Viresh Kumar, Lee Jones, Ivan Kokshaysky, Sven Auhagen, and Xin Hao). - Make schedutil default governor for ARM (Valentin Schneider). - Fix dependency issues for imx (Walter Lozano). - Cleanup around cached_resolved_idx in cpufreq core (Viresh Kumar)." * 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm: cpufreq: make schedutil the default for arm and arm64 cpufreq: cached_resolved_idx can not be negative cpufreq: Add Tegra194 cpufreq driver dt-bindings: arm: Add NVIDIA Tegra194 CPU Complex binding cpufreq: imx: Select NVMEM_IMX_OCOTP cpufreq: sti-cpufreq: Fix some formatting and misspelling issues cpufreq: tegra186: Simplify probe return path cpufreq: CPPC: Reuse caps variable in few routines cpufreq: ap806: fix cpufreq driver needs ap cpu clk cpufreq: cppc: Reorder code and remove apply_hisi_workaround variable cpufreq: dt: fix oops on armada37xx cpufreq: brcmstb-avs-cpufreq: send S2_ENTER / S2_EXIT commands to AVS cpufreq: brcmstb-avs-cpufreq: Support polling AVS firmware cpufreq: brcmstb-avs-cpufreq: more flexible interface for __issue_avs_command() cpufreq: qcom: Disable fast switch when scaling DDR/L3 cpufreq: qcom: Update the bandwidth levels on frequency change OPP: Add and export helper to set bandwidth cpufreq: blacklist SC7180 in cpufreq-dt-platdev cpufreq: blacklist SDM845 in cpufreq-dt-platdev 2020-07-30T05:27:51+00:00 Sumit Gupta sumitg@nvidia.com 2020-07-16T08:30:01+00:00 urn:sha1:df320f89359c0cc22ff552da3ffd07171f7754a6 Add support for CPU frequency scaling on Tegra194. The frequency of each core can be adjusted by writing a clock divisor value to a MSR on the core. The range of valid divisors is queried from the BPMP. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> 2020-07-01T09:10:18+00:00 Mike Rapoport rppt@linux.ibm.com 2020-06-10T06:57:50+00:00 urn:sha1:5853d602dc581b891cc591ec5f67024bcaacdfcf The unicore32 port is removed from the kernel. There is no point to keep stale cpufreq driver for this architecture. Signed-off-by: Mike Rapoport <rppt@linux.ibm.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Guenter Roeck <linux@roeck-us.net> 2019-10-21T10:53:58+00:00 Sudeep Holla sudeep.holla@arm.com 2019-10-21T10:20:34+00:00 urn:sha1:a0f950d3a0addc9552233aa2ffbdc086aa02106a arm_big_little cpufreq driver was designed as a generic big little driver that could be used by any platform and make use of bL switcher. Over years alternate solutions have been designed and merged to deal with bL/HMP systems like EAS. Also since no other driver made use of generic arm_big_little cpufreq driver except Vexpress SPC, we can merge them together as vexpress-spc driver used only on Vexpress TC2(CA15_CA7) platform. Acked-by: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> 2019-09-03T02:25:22+00:00 Viresh Kumar viresh.kumar@linaro.org 2019-09-03T02:25:22+00:00 urn:sha1:f75d2accca7785657311653c125bb22f342dc5d9 2019-09-03T02:25:00+00:00 Sricharan R sricharan@codeaurora.org 2019-07-25T10:41:31+00:00 urn:sha1:7d12709544b8b3fb9727a34a664b8380e1e3493a The kryo cpufreq driver reads the nvmem cell and uses that data to populate the opps. There are other qcom cpufreq socs like krait which does similar thing. Except for the interpretation of the read data, rest of the driver is same for both the cases. So pull the common things out for reuse. Signed-off-by: Sricharan R <sricharan@codeaurora.org> [niklas.cassel@linaro.org: split dt-binding into a separate patch and do not rename the compatible string. Update MAINTAINERS file.] Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Ilia Lin <ilia.lin@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> 2019-07-22T05:40:51+00:00 Yangtao Li tiny.windzz@gmail.com 2019-06-12T16:28:15+00:00 urn:sha1:f328584f7bff86858249bb358f1adcecde48388a For some SoCs, the CPU frequency subset and voltage value of each OPP varies based on the silicon variant in use. The sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to provide the OPP framework with required information. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> 2019-06-13T03:28:22+00:00 Nicolas Saenz Julienne nsaenzjulienne@suse.de 2019-06-12T18:24:56+00:00 urn:sha1:d3df18a97e586702920337056540267807b23f8e Raspberry Pi's firmware offers and interface though which update it's performance requirements. It allows us to request for specific runtime frequencies, which the firmware might or might not respect, depending on the firmware configuration and thermals. As the maximum and minimum frequencies are configurable in the firmware there is no way to know in advance their values. So the Raspberry Pi cpufreq driver queries them, builds an opp frequency table to then launch cpufreq-dt. Also, as the firmware interface might be configured as a module, making the cpu clock unavailable during init, this implements a full fledged driver, as opposed to most drivers registering cpufreq-dt, which only make use of an init routine. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Acked-by: Eric Anholt <eric@anholt.net> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> 2019-05-20T07:17:48+00:00 Leonard Crestez leonard.crestez@nxp.com 2019-05-13T11:01:38+00:00 urn:sha1:4d28ba1d62c48d5242ca30fa0051ab3498bc5c5b Right now in upstream imx8m cpufreq support just lists a common subset of OPPs because the higher ones should only be attempted after checking speed grading in fuses. Add a small driver which checks speed grading from nvmem cells before registering cpufreq-dt. This driver allows unlocking all frequencies for imx8mm and imx8mq and could be applied to other chips like imx7d Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> 2019-02-07T04:31:51+00:00 Gregory CLEMENT gregory.clement@bootlin.com 2019-01-18T14:51:01+00:00 urn:sha1:f525a670533d961fd72ab748e3aac002d7b3d1b9 Add cpufreq driver for Marvell AP-806 found on Aramda 8K. The AP-806 has DFS (Dynamic Frequency Scaling) with coupled clock domain for two clusters, so this driver will directly use generic cpufreq-dt driver as backend. Based on the work of Omri Itach <omrii@marvell.com>. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>