kernel/linux.git/drivers/clocksource/timer-tegra186.c, branch v7.2-rc1

clocksource/drivers/timer-tegra186: Reserve and service a kernel watchdog

2026-06-10T05:25:54+00:00

Tegra SoCs supports multiple watchdog timers. If the kernel crashes or hangs before userspace enables a watchdog, the system cannot recover and may remain bricked, e.g. after a failed OTA update. The driver currently leaves all watchdogs disabled until userspace configures them. Reserve first available watchdog as a kernel-only watchdog for Tegra186 and Tegra234. Arm it during probe (120s timeout) and keep it alive in the driver IRQ handler. Do not register it to userspace. Other available watchdogs remain exposed to userspace. This guarantees the system can reset itself in case of a hang or crash even when userspace never starts. Signed-off-by: Kartik Rajput Signed-off-by: Daniel Lezcano Reviewed-by: Jon Hunter Link: https://patch.msgid.link/20260507154557.2082697-5-kkartik@nvidia.com

clocksource/drivers/timer-tegra186: Register all accessible watchdog timers

2026-06-10T05:25:40+00:00

Tegra186+ SoCs expose multiple watchdog timers, but the driver only registers WDT(0). Iterate over num_wdts and, for each WDT, check the SCR (firewall) registers in the TKE block to determine whether Linux has read and write access. Register the watchdogs that are accessible. Signed-off-by: Kartik Rajput Signed-off-by: Daniel Lezcano Reviewed-by: Jon Hunter Link: https://patch.msgid.link/20260507154557.2082697-4-kkartik@nvidia.com

clocksource/drivers/timer-tegra186: Correct num_wdts for Tegra186 and Tegra234

2026-06-10T05:25:26+00:00

On Tegra186 and Tegra234, WDT2 is connected to the Audio Processing Engine (APE) and cannot be accessed from Linux. Only WDT0 and WDT1 are accessible to Linux. Update num_wdts from 3 to 2 for both Tegra186 and Tegra234 to reflect the actual number of watchdogs available to Linux. Signed-off-by: Kartik Rajput Signed-off-by: Daniel Lezcano Reviewed-by: Jon Hunter Link: https://patch.msgid.link/20260507154557.2082697-3-kkartik@nvidia.com

clocksource/drivers/timer-tegra186: Fix support for multiple watchdog instances

2026-06-10T05:25:08+00:00

Tegra SoCs support multiple watchdogs; currently only one (WDT0) is used. When multiple watchdogs are registered, tegra186_wdt_enable() overwrites the TKEIE(x) register, discarding any existing watchdog interrupt enable bits. As a result, enabling one watchdog inadvertently disables interrupts for the others. Fix this by preserving the existing TKEIE(x) value and updating it using a read-modify-write sequence. Fixes: 42cee19a9f83 ("clocksource: Add Tegra186 timers support") Cc: stable@vger.kernel.org Signed-off-by: Kartik Rajput Signed-off-by: Daniel Lezcano Reviewed-by: Jon Hunter Link: https://patch.msgid.link/20260507154557.2082697-2-kkartik@nvidia.com

clocksource/drivers/timer-tegra186: Don't print superfluous errors

2025-09-23T10:41:39+00:00

The watchdog core will handle error messages already. Signed-off-by: Wolfram Sang Signed-off-by: Daniel Lezcano Reviewed-by: Mikko Perttunen Link: https://lore.kernel.org/r/20250813190657.3628-2-wsa+renesas@sang-engineering.com

clocksource/drivers/tegra186: Avoid 64-bit division

2025-09-23T08:55:12+00:00

The newly added function causes a build failure on 32-bit targets with older compiler version such as gcc-10: arm-linux-gnueabi-ld: drivers/clocksource/timer-tegra186.o: in function `tegra186_wdt_get_timeleft': timer-tegra186.c:(.text+0x3c2): undefined reference to `__aeabi_uldivmod' The calculation can trivially be changed to avoid the division entirely, as USEC_PER_SEC is a multiple of 5. Change both such calculation for consistency, even though gcc apparently managed to optimize the other one properly already. [dlezcano : Fixed conflict with 20250614175556.922159-2-linux@roeck-us.net ] Fixes: 28c842c8b0f5 ("clocksource/drivers/timer-tegra186: Add WDIOC_GETTIMELEFT support") Signed-off-by: Arnd Bergmann Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20250620111939.3395525-1-arnd@kernel.org

clocksource/drivers/timer-tegra186: Simplify calculating timeleft

2025-09-23T08:54:58+00:00

It is not necessary to use 64-bit operations to calculate the remaining watchdog timeout. Simplify to use 32-bit operations, and add comments explaining why there will be no overflow. Signed-off-by: Guenter Roeck Signed-off-by: Daniel Lezcano Reviewed-by: Jon Hunter Cc: Pohsun Su Cc: Robert Lin Link: https://lore.kernel.org/r/20250614175556.922159-2-linux@roeck-us.net

clocksource/drivers/timer-tegra186: Avoid 64-bit divide operation

2025-09-23T08:54:29+00:00

Building the driver on xtensa fails with tensa-linux-ld: drivers/clocksource/timer-tegra186.o: in function `tegra186_timer_remove': timer-tegra186.c:(.text+0x350): undefined reference to `__udivdi3' Avoid the problem by rearranging the offending code to avoid the 64-bit divide operation. Fixes: 28c842c8b0f5 ("clocksource/drivers/timer-tegra186: Add WDIOC_GETTIMELEFT support") Signed-off-by: Guenter Roeck Signed-off-by: Daniel Lezcano Reviewed-by: Jon Hunter Cc: Pohsun Su Cc: Robert Lin Link: https://lore.kernel.org/r/20250614175556.922159-1-linux@roeck-us.net

clocksource/drivers/tegra186: Add module owner

2025-09-23T08:52:04+00:00

The conversion to modules requires a correct handling of the module refcount in order to prevent to unload it if it is in use. That is especially true with the clockevents where there is no function to unregister them. The core time framework correctly handles the module refcount with the different clocksource and clockevents if the module owner is set. Add the module owner to make sure the core framework will prevent stupid things happening when the driver will be converted into a module. Signed-off-by: Daniel Lezcano Reviewed-by: Will McVicker Link: https://lore.kernel.org/r/20250602151853.1942521-5-daniel.lezcano@linaro.org

clocksource/drivers/timer-tegra186: Remove unused bits

2025-05-16T09:10:33+00:00

The intention to keep the unsed if(0) block is gone now. Remove them for clean codes. Signed-off-by: robelin Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20250507044311.3751033-4-robelin@nvidia.com Signed-off-by: Daniel Lezcano