Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v6.12.80 2022-12-02T11:48:28+00:00 2022-12-02T11:48:28+00:00 Jonathan Neuschäfer j.neuschaefer@gmx.net 2022-11-04T16:18:46+00:00 urn:sha1:db78539fc95cf62b0b8f274368fcd8202eac91f9 In the WPCM450 SoC, the clocks for each timer can be gated individually. To prevent the timer 1 clock from being gated, enable it explicitly. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20221104161850.2889894-3-j.neuschaefer@gmx.net Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org> 2021-04-08T11:24:16+00:00 Jonathan Neuschäfer j.neuschaefer@gmx.net 2021-03-20T18:16:06+00:00 urn:sha1:690daddcb60246d8a510aaad7b954bcc53eba17e Add a compatible string for WPCM450, which has essentially the same timer controller. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20210320181610.680870-11-j.neuschaefer@gmx.net 2019-08-26T22:31:39+00:00 Avi Fishman avifishman70@gmail.com 2019-07-29T17:03:54+00:00 urn:sha1:a2b58537b4a1cc08fd254fb8d1c24191ce286ae1 NPCM7XX_Tx_OPER GENMASK bits are wrong, fix them. Hopefully the NPCM7XX_REG_TICR0 register reset value of those bits was 0, so it did not cause an issue. The function npcm7xx_timer_oneshot() reads the register NPCM7XX_REG_TCSR0, modifies it and then reads it again overwriting the previous changes. Remove the extra read which is pointless. The function npcm7xx_timer_periodic() is correct but the code writes to the NPCM7XX_REG_TICR0 register while it is dealing with the NPCM7XX_REG_TCSR0 register, that is confusing. Separate the write to the registers in the code for the sake of clarity. Fixes: 1c00289ecd12 ("clocksource/drivers/npcm: Add NPCM7xx timer driver") Signed-off-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> 2019-07-10T09:05:26+00:00 Joe Perches joe@perches.com 2019-07-10T05:04:15+00:00 urn:sha1:9bdd7bb3a8447fe841cd37ddd9e0a6974b06a0bb Arguments are supposed to be ordered high then low. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/d6a9d49c9837d38816b71d783f5aed7235e8ca94.1562734889.git.joe@perches.com 2018-03-30T20:44:09+00:00 Tomer Maimon tmaimon77@gmail.com 2018-03-08T15:24:58+00:00 urn:sha1:1c00289ecd12471ba9733e61aaf1d39883a77b16 Add Nuvoton BMC NPCM7xx timer driver. The clocksource Enable 24-bit TIMER0 and TIMER1 counters, while TIMER0 serve as clockevent and TIMER1 serve as clocksource. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Brendan Higgins <brendanhiggins@xxxxxxxxxx> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>