kernel/linux.git/drivers/clocksource/mips-gic-timer.c, branch v6.12.80

clocksource: mips-gic-timer: Enable counter when CPUs start

2025-05-29T09:02:41+00:00

[ Upstream commit 3128b0a2e0cf6e07aa78e5f8cf7dd9cd59dc8174 ] In multi-cluster MIPS I6500 systems there is a GIC in each cluster, each with its own counter. When a cluster powers up the counter will be stopped, with the COUNTSTOP bit set in the GIC_CONFIG register. In single cluster systems, it has been fine to clear COUNTSTOP once in gic_clocksource_of_init() to start the counter. In multi-cluster systems, this will only have started the counter in the boot cluster, and any CPUs in other clusters will find their counter stopped which will break the GIC clock_event_device. Resolve this by having CPUs clear the COUNTSTOP bit when they come online, using the existing gic_starting_cpu() CPU hotplug callback. This will allow CPUs in secondary clusters to ensure that the cluster's GIC counter is running as expected. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo Reviewed-by: Philippe Mathieu-Daudé Tested-by: Serge Semin Tested-by: Gregory CLEMENT Acked-by: Daniel Lezcano Signed-off-by: Thomas Bogendoerfer Signed-off-by: Sasha Levin

clocksource/drivers/mips-gic-timer: Correct sched_clock width

2024-07-12T14:07:05+00:00

Counter width of GIC is configurable and can be read from a register. Use width value from the register for sched_clock. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Jiaxun Yang Link: https://lore.kernel.org/r/20240612-mips-clks-v2-7-a57e6f49f3db@flygoat.com Signed-off-by: Daniel Lezcano

clocksource/drivers/mips-gic-timer: Refine rating computation

2024-07-12T14:07:05+00:00

It is a good clocksource which usually go as fast as CPU core and have a low access latency, so raise the base of rating from Good to desired when we know that it has a stable frequency. Increase frequency addend dividend to 10000000 (10MHz) to reasonably accommodate multi GHz level clock, also cap rating within current level. Signed-off-by: Jiaxun Yang Link: https://lore.kernel.org/r/20240612-mips-clks-v2-6-a57e6f49f3db@flygoat.com Signed-off-by: Daniel Lezcano

clocksource/drivers/mips-gic-timer: Convert to SPDX identifier

2022-05-18T09:08:59+00:00

The licensing text references explicitely the COPYING file in the kernel base directory, which is clearly GPL version 2 only. Signed-off-by: Thomas Gleixner Cc: Thomas Bogendoerfer Cc: Serge Semin Cc: Daniel Lezcano Cc: linux-mips@vger.kernel.org Acked-by: Serge Semin Link: https://lore.kernel.org/r/20220510171254.529249404@linutronix.de Signed-off-by: Daniel Lezcano

clocksource: mips-gic-timer: Mark GIC timer as unstable if ref clock changes

2020-05-22T22:03:16+00:00

Currently clocksource framework doesn't support the clocks with variable frequency. Since MIPS GIC timer ticks rate might be unstable on some platforms, we must make sure that it justifies the clocksource requirements. MIPS GIC timer is incremented with the CPU cluster reference clocks rate. So in case if CPU frequency changes, the MIPS GIC tick rate changes synchronously. Due to this the clocksource subsystem can't rely on the timer to measure system clocks anymore. This commit marks the MIPS GIC based clocksource as unstable if reference clock (normally it's a CPU reference clocks) rate changes. The clocksource will execute a watchdog thread, which lowers the MIPS GIC timer rating to zero and fallbacks to a new stable one. Note we don't need to set the CLOCK_SOURCE_MUST_VERIFY flag to the MIPS GIC clocksource since normally the timer is stable. The only reason why it gets unstable is due to the ref clock rate change, which event we detect here in the driver by means of the clocks event notifier. Signed-off-by: Serge Semin Cc: Alexey Malahov Cc: Thomas Bogendoerfer Cc: Paul Burton Cc: Ralf Baechle Cc: Alessandro Zummo Cc: Alexandre Belloni Cc: Arnd Bergmann Cc: Rob Herring Cc: linux-mips@vger.kernel.org Cc: linux-rtc@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20200521204818.25436-9-Sergey.Semin@baikalelectronics.ru

clocksource: mips-gic-timer: Register as sched_clock

2020-05-22T22:03:08+00:00

The MIPS GIC timer is well suited for use as sched_clock, so register it as such. Whilst the existing gic_read_count() function matches the prototype needed by sched_clock_register() already, we split it into 2 functions in order to remove the need to evaluate the mips_cm_is64 condition within each call since sched_clock should be as fast as possible. Note the sched clock framework needs the clock source being stable in order to rely on it. So we register the MIPS GIC timer as schedule clocks only if it's, if either the system doesn't have CPU-frequency enabled or the CPU frequency is changed by means of the CPC core clock divider available on the platforms with CM3 or newer. Signed-off-by: Paul Burton Co-developed-by: Serge Semin [Sergey.Semin@baikalelectronics.ru: Register sched-clock if CM3 or !CPU-freq] Signed-off-by: Serge Semin Cc: Alexey Malahov Cc: Thomas Bogendoerfer Cc: Ralf Baechle Cc: Alessandro Zummo Cc: Alexandre Belloni Cc: Arnd Bergmann Cc: Rob Herring Cc: linux-mips@vger.kernel.org Cc: linux-rtc@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20200521204818.25436-8-Sergey.Semin@baikalelectronics.ru

mips: vdso: Use generic VDSO clock mode storage

2020-02-17T19:12:16+00:00

Switch to the generic VDSO clock mode storage. Signed-off-by: Thomas Gleixner Reviewed-by: Vincenzo Frascino Link: https://lkml.kernel.org/r/20200207124403.244684017@linutronix.de

clocksource/drivers/mips-gic-timer: Make gic_compare_irqaction static

2019-03-22T21:59:33+00:00

Fix sparse warning: drivers/clocksource/mips-gic-timer.c:70:18: warning: symbol 'gic_compare_irqaction' was not declared. Should it be static? Signed-off-by: YueHaibing Signed-off-by: Thomas Gleixner Cc: Link: https://lkml.kernel.org/r/20190322144359.19516-1-yuehaibing@huawei.com

clocksource/drivers/mips-gic-timer: Add pr_fmt and reword pr_* messages

2018-05-18T20:53:09+00:00

Several messages from the MIPS GIC driver include the text "GIC", "GIC timer", etc, but the format is not standard. Add a pr_fmt of "mips-gic-timer: " and reword the messages now that they will be prefixed with the driver name. Signed-off-by: Matt Redfearn Signed-off-by: Daniel Lezcano

clocksource/drivers/mips-gic-timer: Use correct shift count to extract data

2018-02-28T12:55:14+00:00

__gic_clocksource_init() extracts the GIC_CONFIG_COUNTBITS field from read_gic_config() by right shifting the register value. The shift count is determined by the most significant bit (__fls) of the bitmask which is wrong as it shifts out the complete bitfield. Use the least significant bit (__ffs) instead to shift the bitfield down to bit 0. Fixes: e07127a077c7 ("clocksource: mips-gic-timer: Use new GIC accessor functions") Signed-off-by: Felix Fietkau Signed-off-by: Thomas Gleixner Cc: daniel.lezcano@linaro.org Cc: paul.burton@imgtec.com Link: https://lkml.kernel.org/r/20180228095610.50341-1-nbd@nbd.name