kernel/linux.git/drivers/clocksource/Makefile, branch v6.19.11

clocksource/drivers: Add Realtek system timer driver

2025-11-26T10:25:15+00:00

Add a system timer driver for Realtek SoCs. This driver registers the 1 MHz global hardware counter on Realtek platforms as a clock event device. Since this hardware counter starts counting automatically after SoC power-on, no clock initialization is required. Because the counter does not stop or get affected by CPU power down, and it supports oneshot mode, it is typically used as a tick broadcast timer. Signed-off-by: Hao-Wen Ting Signed-off-by: Daniel Lezcano Acked-by: Thomas Gleixner Link: https://patch.msgid.link/20251126060110.198330-3-haowen.ting@realtek.com

clocksource/drivers/arm_arch_timer_mmio: Switch over to standalone driver

2025-09-23T10:31:50+00:00

Remove all the MMIO support from the per-CPU timer driver, and switch over to the standalove driver. Signed-off-by: Marc Zyngier Signed-off-by: Daniel Lezcano Tested-by: Sudeep Holla Reviewed-by: Sudeep Holla Link: https://lore.kernel.org/r/20250814154622.10193-4-maz@kernel.org

clocksource/drivers/vf-pit: Rename the VF PIT to NXP PIT

2025-09-23T10:30:05+00:00

The PIT acronym stands for Periodic Interrupt Timer which is found on different NXP platforms not only on the Vybrid Family. Change the name to be more generic for the NXP platforms in general. That will be consistent with the NXP STM driver naming convention. Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20250804152344.1109310-19-daniel.lezcano@linaro.org

clocksource/drivers: Add EcoNet Timer HPT driver

2025-05-16T09:10:33+00:00

Introduce a clocksource driver for the so-called high-precision timer (HPT) in the EcoNet EN751221 and EN751627 MIPS SoCs. It's a 32 bit upward-counting one-shot timer which relies on the crystal so it is unaffected by CPU power mode. On MIPS 34K devices (single core) there is one timer, and on 1004K devices (dual core) there are two. Each timer has two sets of count/compare registers so that there is one for each of the VPEs on the core. Because each core has 2 VPEs, register selection takes the CPU number / 2 for the timer corrisponding to the core, then CPU number % 2 for the register corrisponding to the VPE. These timers use a percpu-devid IRQ to route interrupts to the VPE which set the event. Signed-off-by: Caleb James DeLisle Link: https://lore.kernel.org/r/20250507134500.390547-3-cjd@cjdns.fr Signed-off-by: Daniel Lezcano

clocksource/drivers/nxp-timer: Add the System Timer Module for the s32gx platforms

2025-05-16T09:10:32+00:00

STM supports commonly required system and application software timing functions. STM includes a 32-bit count-up timer and four 32-bit compare channels with a separate interrupt source for each channel. The timer is driven by the STM module clock divided by an 8-bit prescale value (1 to 256). STM has the following features: • One 32-bit count-up timer with an 8-bit prescaler • Four 32-bit compare channels • An independent interrupt source for each channel • Ability to stop the timer in Debug mode The s32g platform is declined into two versions, the s32g2 and the s32g3. The former has a STM block with 8 timers and the latter has 12 timers. The platform is designed to have one usable STM instance per core on the system which is composed of 3 x Cortex-M3 + 4 Cortex-A53 for the s32g2 and 3 x Cortex-M3 + 8 Cortex-A53 for the s32g3. There is a special STM instance called STM_TS which is dedicated to the timestamp. The 7th STM instance STM_07 is directly tied to the STM_TS which means it is not usable as a clockevent. The driver instantiate each STM described in the device tree as a clocksource and a clockevent conforming to the reference manual even if the Linux system does not use all of the clocksource. Each clockevent will have a cpumask set for a specific CPU. Given the counter is shared between the clocksource and the clockevent, the STM module can not be disabled by one or another so the refcounting mechanism is used to stop the counter when it reaches zero and to start it when it is one. The suspend and resume relies on the refcount to stop the module. As the device tree will have multiple STM entries, the driver can be probed in parallel with the async option but it is not enabled yet. However, the driver code takes care of preventing a race by putting a lock to protect the number of STM instances global variable which means it is ready to support the option when enough testing will be done with the underlying time framework. Cc: Ghennadi Procopciuc Cc: Krzysztof Kozlowski Cc: Thomas Fossati Suggested-by: Ghennadi Procopciuc Link: https://lore.kernel.org/r/20250417151623.121109-3-daniel.lezcano@linaro.org Signed-off-by: Daniel Lezcano

clocksource/drivers/ralink: Add Ralink System Tick Counter driver

2024-11-13T12:49:33+00:00

System Tick Counter is present on Ralink SoCs RT3352 and MT7620. This driver has been in 'arch/mips/ralink' directory since the beggining of Ralink architecture support. However, it can be moved into a more proper place in 'drivers/clocksource'. Hence add it here adding also support for compile test targets and reducing LOC in architecture code folder. Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20241028203643.191268-2-sergio.paracuellos@gmail.com Signed-off-by: Daniel Lezcano

clocksource/drivers/realtek: Add timer driver for rtl-otto platforms

2024-07-12T14:07:06+00:00

The timer/counter block on the Realtek SoCs provides up to 5 timers. It also includes a watchdog timer which is handled by the realtek_otto_wdt.c driver. One timer will be used per CPU as a local clock event generator. An additional timer will be used as an overal stable clocksource. Signed-off-by: Markus Stockhausen Signed-off-by: Sander Vanheule Signed-off-by: Chris Packham Link: https://lore.kernel.org/r/20240710043524.1535151-8-chris.packham@alliedtelesis.co.nz Signed-off-by: Daniel Lezcano

clocksource: ep93xx: Add driver for Cirrus Logic EP93xx

2023-10-15T21:36:36+00:00

Rewrite EP93xx timer driver located in arch/arm/mach-ep93xx/timer-ep93xx.c trying to do everything the device tree way: - Make every IO-access relative to a base address and dynamic so we can do a dynamic ioremap and get going. - Find register range and interrupt from the device tree. Reviewed-by: Linus Walleij Tested-by: Alexander Sverdlin Signed-off-by: Nikita Shubin Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20230915-ep93xx-v4-12-a1d779dcec10@maquefel.me

clocksource/drivers/timer-oxnas-rps: Remove obsolete timer driver

2023-07-13T12:46:17+00:00

Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 timer. Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong Acked-by: Andy Shevchenko Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20230630-topic-oxnas-upstream-remove-v2-3-fb6ab3dea87c@linaro.org

clocksource/drivers/loongson1: Move PWM timer to clocksource framework

2023-06-19T15:07:03+00:00

This patch moves most part of arch/mips/loongson32/common/time.c into drivers/clocksource. Adapt the driver to clocksource framework with devicetree support and updates Kconfig/Makefile options. Signed-off-by: Keguang Zhang Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20230512103724.587760-4-keguang.zhang@gmail.com