kernel/linux.git/drivers/clk, branch linux-4.20.y

clk: qcom: gcc: Use active only source for CPUSS clocks

2019-03-13T21:04:01+00:00

[ Upstream commit 9ff1a3b4912528f853048ccd9757ba6a2cc75557 ] The clocks of the CPUSS such as "gcc_cpuss_ahb_clk_src" is a CRITICAL clock and needs to vote on the active only source of XO, so as to keep the vote as long as CPUSS is active. Similar rbcpr_clk_src is also has the same requirement. Signed-off-by: Taniya Das Fixes: 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845") Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: ti: Fix error handling in ti_clk_parse_divider_data()

2019-03-13T21:04:01+00:00

[ Upstream commit 303aef8b84272d73999a3207dd05bbe10ed89dc5 ] The ti_clk_parse_divider_data() function is only called from _get_div_table_from_setup(). That function doesn't look at the return value but instead looks at the "*table" pointer. In this case, if the kcalloc() fails then *table is NULL (which means success). It should instead be an error pointer. The ti_clk_parse_divider_data() function has two callers. One checks for errors and the other doesn't. I have fixed it so now both handle errors. Fixes: 4f6be5655dc9 ("clk: ti: divider: add driver internal API for parsing divider data") Signed-off-by: Dan Carpenter Acked-by: Tero Kristo Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: vc5: Abort clock configuration without upstream clock

2019-03-05T16:59:35+00:00

[ Upstream commit 2137a109a5e39c2bdccfffe65230ed3fadbaac0e ] In case the upstream clock are not set, which can happen in case the VC5 has no valid upstream clock, the $src variable is used uninited by regmap_update_bits(). Check for this condition and return -EINVAL in such case. Note that in case the VC5 has no valid upstream clock, the VC5 can not operate correctly. That is a hardware property of the VC5. The internal oscilator present in some VC5 models is also considered upstream clock. Signed-off-by: Marek Vasut Cc: Alexey Firago Cc: Laurent Pinchart Cc: Stephen Boyd Cc: linux-renesas-soc@vger.kernel.org [sboyd@kernel.org: Added comment about probe preventing this from happening in the first place] Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: sysfs: fix invalid JSON in clk_dump

2019-03-05T16:59:35+00:00

[ Upstream commit c6e909972ef87aa2a479269f46b84126f99ec6db ] Add a missing comma so that the output is valid JSON format again. Fixes: 9fba738a53dd ("clk: add duty cycle support") Signed-off-by: Lubomir Rintel Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: tegra: dfll: Fix a potential Oop in remove()

2019-03-05T16:59:35+00:00

[ Upstream commit d39eca547f3ec67140a5d765a426eb157b978a59 ] If tegra_dfll_unregister() fails then "soc" is an error pointer. We should just return instead of dereferencing it. Fixes: 1752c9ee23fb ("clk: tegra: dfll: Fix drvdata overwriting issue") Signed-off-by: Dan Carpenter Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: at91: fix at91sam9x5 peripheral clock number

2019-02-27T09:09:54+00:00

commit 1b328a2e095a009518ebac05e937cc0fc242fede upstream. nck() looks at the last id in an array and unfortunately, at91sam9x35_periphck has a sentinel, hence the id is 0 and the calculated number of peripheral clocks is 1 instead of a maximum of 31. Fixes: 1eabdc2f9dd8 ("clk: at91: add at91sam9x5 PMCs driver") Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre Cc: # v4.20+ Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

clk: at91: fix masterck name

2019-02-27T09:09:54+00:00

commit 65a91e2e597dea62a798a8b771edc44859037e7f upstream. The master clock is actually named masterck earlier in the driver. Having "mck" in the parent list means that it can never be selected. Fixes: 1eabdc2f9dd8 ("clk: at91: add at91sam9x5 PMCs driver") Fixes: a2038077de9a ("clk: at91: add sama5d2 PMC driver") Fixes: 084b696bb509 ("clk: at91: add sama5d4 pmc driver") Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre Cc: # v4.20+ Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

clk: qcom: Leave mmss noc on for 8998

2019-02-12T19:02:19+00:00

[ Upstream commit 12eced09cd301aa7b1868a67c50a651c2aacd363 ] Similar to other qcom targets, gcc_mmss_noc_cfg_ahb_clk should not be disabled. Any mmss access depends on this clock, and its been observed that enabling mmssnoc_axi_rpm_clk with rpmcc results in an implicit access to mmss and will crash the system if gcc_mmss_noc_cfg_ahb_clk is disabled. Signed-off-by: Jeffrey Hugo Fixes: 4807c71cc688 (arm64: dts: Add msm8998 SoC and MTP board support) Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: imx6sl: ensure MMDC CH0 handshake is bypassed

2019-02-12T19:02:17+00:00

[ Upstream commit 0efcc2c0fd2001a83240a8c3d71f67770484917e ] Same as other i.MX6 SoCs, ensure unused MMDC channel's handshake is bypassed, this is to make sure no request signal will be generated when periphe_clk_sel is changed or SRC warm reset is triggered. Signed-off-by: Anson Huang Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin

clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks

2019-02-12T19:02:14+00:00

[ Upstream commit 6e6da2039c82271dd873b9ad2b902a692a7dd554 ] All the audio interfaces on Allwinner SoCs need to change their module clocks during operation, to switch between support for 44.1 kHz and 48 kHz family sample rates. The clock rate for the module clocks is governed by their upstream audio PLL. The module clocks themselves only have a gate, and sometimes a divider or mux. Thus any rate changes need to be propagated upstream. Set the CLK_SET_RATE_PARENT flag for all audio module clocks to achieve this. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard Signed-off-by: Sasha Levin