<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/clk/x86, branch linux-5.11.y</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=linux-5.11.y</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=linux-5.11.y'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2020-08-15T15:18:22+00:00</updated>
<entry>
<title>Merge tag 'acpi-5.9-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm</title>
<updated>2020-08-15T15:18:22+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2020-08-15T15:18:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=341323fa0eed1b201130b7af84d40fa04725c832'/>
<id>urn:sha1:341323fa0eed1b201130b7af84d40fa04725c832</id>
<content type='text'>
Pull more ACPI updates from Rafael Wysocki:
 "Add new hardware support to the ACPI driver for AMD SoCs, the x86 clk
  driver and the Designware i2c driver (changes from Akshu Agrawal and
  Pu Wen)"

* tag 'acpi-5.9-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm:
  clk: x86: Support RV architecture
  ACPI: APD: Add a fmw property is_raven
  clk: x86: Change name from ST to FCH
  ACPI: APD: Change name from ST to FCH
  i2c: designware: Add device HID for Hygon I2C controller
</content>
</entry>
<entry>
<title>clk: x86: Support RV architecture</title>
<updated>2020-08-07T18:12:00+00:00</updated>
<author>
<name>Akshu Agrawal</name>
<email>akshu.agrawal@amd.com</email>
</author>
<published>2020-07-31T13:36:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=19fe87fd854a92c746ac73cb91a0bebac07a4618'/>
<id>urn:sha1:19fe87fd854a92c746ac73cb91a0bebac07a4618</id>
<content type='text'>
There is minor difference between previous family of SoC and
the current one. Which is the there is only 48Mh fixed clk.
There is no mux and no option to select another freq as there in previous.

Signed-off-by: Akshu Agrawal &lt;akshu.agrawal@amd.com&gt;
Reviewed-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>clk: x86: Change name from ST to FCH</title>
<updated>2020-08-07T18:11:59+00:00</updated>
<author>
<name>Akshu Agrawal</name>
<email>akshu.agrawal@amd.com</email>
</author>
<published>2020-07-31T13:36:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d9b77361c1a5155e3d803d4ce9d7010269d301d3'/>
<id>urn:sha1:d9b77361c1a5155e3d803d4ce9d7010269d301d3</id>
<content type='text'>
AMD SoC general pupose clk is present in new platforms with
minor differences. We can reuse the same clk driver for other
platforms. Hence, changing name from ST(SoC) to FCH(IP)

Signed-off-by: Akshu Agrawal &lt;akshu.agrawal@amd.com&gt;
Reviewed-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>ACPI: APD: Change name from ST to FCH</title>
<updated>2020-08-07T18:11:59+00:00</updated>
<author>
<name>Akshu Agrawal</name>
<email>akshu.agrawal@amd.com</email>
</author>
<published>2020-07-31T13:36:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d58669b093997e4e5f98c38a54f99761657c19d2'/>
<id>urn:sha1:d58669b093997e4e5f98c38a54f99761657c19d2</id>
<content type='text'>
AMD SoC general pupose clk is present in new platforms with
same MMIO mappings. We can reuse the same clk handler support
for other platforms. Hence, changing name from ST(SoC) to FCH(IP)

Signed-off-by: Akshu Agrawal &lt;akshu.agrawal@amd.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
</entry>
<entry>
<title>clk: intel: Avoid unnecessary memset by improving code</title>
<updated>2020-07-24T08:58:15+00:00</updated>
<author>
<name>Rahul Tanwar</name>
<email>rahul.tanwar@linux.intel.com</email>
</author>
<published>2020-07-16T06:30:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d310124cd99df5e5011d79f36a6d16d3452de348'/>
<id>urn:sha1:d310124cd99df5e5011d79f36a6d16d3452de348</id>
<content type='text'>
memset can be avoided in a loop if the variables used are declared
inside the loop. Move such variables declaration inside the loop
to avoid memset.

Signed-off-by: Rahul Tanwar &lt;rahul.tanwar@linux.intel.com&gt;
Link: https://lore.kernel.org/r/26624b65d0e6b958c4765a406b9929d1a9ce1c2c.1594880946.git.rahul.tanwar@linux.intel.com
[sboyd@kernel.org: Drop NULL assignment that is overwritten]
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: intel: Improve locking in the driver</title>
<updated>2020-07-24T08:55:18+00:00</updated>
<author>
<name>Rahul Tanwar</name>
<email>rahul.tanwar@linux.intel.com</email>
</author>
<published>2020-07-16T06:30:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=c9e28fe649f76ee13a9bcc09f89ae0189f85801b'/>
<id>urn:sha1:c9e28fe649f76ee13a9bcc09f89ae0189f85801b</id>
<content type='text'>
Remove/reduce unnecessary spin locking of the code.

Signed-off-by: Rahul Tanwar &lt;rahul.tanwar@linux.intel.com&gt;
Link: https://lore.kernel.org/r/79c0f5f9f5bc512a7e2b5f3c91f6341f28b5854c.1594880946.git.rahul.tanwar@linux.intel.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: intel: Use devm_clk_hw_register() instead of clk_hw_register()</title>
<updated>2020-07-24T08:55:18+00:00</updated>
<author>
<name>Rahul Tanwar</name>
<email>rahul.tanwar@linux.intel.com</email>
</author>
<published>2020-07-16T06:30:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=8529fc0aaa704c6618e69e8d35834aa977b6ece9'/>
<id>urn:sha1:8529fc0aaa704c6618e69e8d35834aa977b6ece9</id>
<content type='text'>
To ensure that clks are unregistered in case of any failure, use
devm_clk_hw_register() instead of clk_hw_register().

Signed-off-by: Rahul Tanwar &lt;rahul.tanwar@linux.intel.com&gt;
Link: https://lore.kernel.org/r/7ef7009b4e9f986fd6dfbf487c0e85de68a4ba9b.1594880946.git.rahul.tanwar@linux.intel.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: intel: remove redundant initialization of variable rate64</title>
<updated>2020-05-28T23:00:33+00:00</updated>
<author>
<name>Colin Ian King</name>
<email>colin.king@canonical.com</email>
</author>
<published>2020-05-28T22:12:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d036466330d13039a09e407b23a0dabec1a9533a'/>
<id>urn:sha1:d036466330d13039a09e407b23a0dabec1a9533a</id>
<content type='text'>
The variable rate64 is being initialized with a value that is never read
and it is being updated later with a new value.  The initialization is
redundant and can be removed.

Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King &lt;colin.king@canonical.com&gt;
Link: https://lkml.kernel.org/r/20200528221219.535804-1-colin.king@canonical.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: intel: Add CGU clock driver for a new SoC</title>
<updated>2020-05-27T02:58:52+00:00</updated>
<author>
<name>Rahul Tanwar</name>
<email>rahul.tanwar@linux.intel.com</email>
</author>
<published>2020-04-17T05:54:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d058fd9e8984cd9f18564f7fec38e07ce671c8b8'/>
<id>urn:sha1:d058fd9e8984cd9f18564f7fec38e07ce671c8b8</id>
<content type='text'>
Clock Generation Unit(CGU) is a new clock controller IP of a forthcoming
Intel network processor SoC named Lightning Mountain(LGM). It provides
programming interfaces to control &amp; configure all CPU &amp; peripheral clocks.
Add common clock framework based clock controller driver for CGU.

Signed-off-by: Rahul Tanwar &lt;rahul.tanwar@linux.intel.com&gt;
Link: https://lkml.kernel.org/r/42a4f71847714df482bacffdcd84341a4052800b.1587102634.git.rahul.tanwar@linux.intel.com
[sboyd@kernel.org: Kill init function to alloc and cleanup newline]
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500</title>
<updated>2019-06-19T15:09:55+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-06-04T08:11:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d2912cb15bdda8ba4a5dd73396ad62641af2f520'/>
<id>urn:sha1:d2912cb15bdda8ba4a5dd73396ad62641af2f520</id>
<content type='text'>
Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Enrico Weigelt &lt;info@metux.net&gt;
Reviewed-by: Kate Stewart &lt;kstewart@linuxfoundation.org&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
</feed>
