kernel/linux.git/drivers/clk/tegra, branch v5.15.7

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2021-09-02T21:17:24+00:00

Pull clk updates from Stephen Boyd: "Nothing changed in the clk framework core this time around. We did get some updates to the basic clk types to use determine_rate for the divider type and add a power of two fractional divider flag though. Otherwise, this is a collection of clk driver updates. More than half the diffstat is in the Qualcomm clk driver where we add a bunch of data to describe clks on various SoCs and fix bugs. The other big new thing in here is the Mediatek MT8192 clk driver. That's been under review for a while and it's nice to see that it's finally upstream. Beyond that it's the usual set of minor fixes and tweaks to clk drivers. There are some non-clk driver bits in here which have all been acked by the respective maintainers. New Drivers: - Support video, gpu, display clks on qcom sc7280 SoCs - GCC clks on qcom MSM8953, SM4250/6115, and SM6350 SoCs - Multimedia clks (MMCC) on qcom MSM8994/MSM8992 - RPMh clks on qcom SM6350 SoCs - Support for Mediatek MT8192 SoCs - Add display (DU and DSI) clocks on Renesas R-Car V3U - Add I2C, DMAC, USB, sound (SSIF-2), GPIO, CANFD, and ADC clocks and resets on Renesas RZ/G2L Updates: - Support the SD/OE pin on IDT VersaClock 5 and 6 clock generators - Add power of two flag to fractional divider clk type - Migrate some clk drivers to clk_divider_ops.determine_rate - Migrate to clk_parent_data in gcc-sdm660 - Fix CLKOUT clocks on i.MX8MM and i.MX8MN by using imx_clk_hw_mux2 - Switch from .round_rate to .determine_rate in clk-divider-gate - Fix clock tree update for TF-A controlled clocks for all i.MX8M - Add missing M7 core clock for i.MX8MN - YAML conversion of rk3399 clock controller binding - Removal of GRF dependency for the rk3328/rk3036 pll types - Drop CLK_IS_CRITICAL flag from Tegra fuse clk - Make CLK_R9A06G032 Kconfig symbol invisible - Convert various DT bindings to YAML" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (128 commits) dt-bindings: clock: samsung: fix header path in example clk: tegra: fix old-style declaration clk: qcom: Add SM6350 GCC driver MAINTAINERS: clock: include S3C and S5P in Samsung SoC clock entry dt-bindings: clock: samsung: convert S5Pv210 AudSS to dtschema dt-bindings: clock: samsung: convert Exynos AudSS to dtschema dt-bindings: clock: samsung: convert Exynos4 to dtschema dt-bindings: clock: samsung: convert Exynos3250 to dtschema dt-bindings: clock: samsung: convert Exynos542x to dtschema dt-bindings: clock: samsung: add bindings for Exynos external clock dt-bindings: clock: samsung: convert Exynos5250 to dtschema clk: vc5: Add properties for configuring SD/OE behavior clk: vc5: Use dev_err_probe dt-bindings: clk: vc5: Add properties for configuring the SD/OE pin dt-bindings: clock: brcm,iproc-clocks: fix armpll properties clk: zynqmp: Fix kernel-doc format clk: at91: clk-generated: Limit the requested rate to our range clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates clk: zynqmp: Fix a memory leak clk: zynqmp: Check the return type ...

clk: tegra: fix old-style declaration

2021-08-29T18:38:11+00:00

With extra warnings enabled, gcc complains about a slightly odd prototype: drivers/clk/tegra/clk-dfll.c:1380:1: error: 'inline' is not at beginning of declaration [-Werror=old-style-declaration] 1380 | static void inline dfll_debug_init(struct tegra_dfll *td) { } Move the 'inline' keyword to the start of the line. Signed-off-by: Arnd Bergmann Link: https://lore.kernel.org/r/20210322215047.1062540-1-arnd@kernel.org Acked-by: Thierry Reding Signed-off-by: Stephen Boyd

clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock

2021-08-11T09:57:01+00:00

FUSE driver now takes care of keeping the clock enabled when necessary. Remove the CLK_IS_CRITICAL flag from the clock. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_ops

2021-07-27T21:54:19+00:00

Implement disable_unused() callback of tegra_clk_sdmmc_mux_ops to fix imbalanced disabling of the unused MMC clock on Tegra210 Jetson Nano. Fixes: c592c8a28f58 ("clk: tegra: Fix refcounting of gate clocks") Reported-by: Jon Hunter # T210 Nano Tested-by: Jon Hunter # T210 Nano Acked-by: Jon Hunter Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20210717112742.7196-1-digetx@gmail.com Signed-off-by: Stephen Boyd

clk: tegra: clk-tegra124-dfll-fcpu: don't use devm functions for regulator

2021-06-25T23:23:07+00:00

The purpose of the device-managed functions is to bind the life-time of an object to that of a parent device object. This is not the case for the 'vdd-cpu' regulator in this driver. A reference is obtained via devm_regulator_get() and immediately released with devm_regulator_put(). In this case, the usage of devm_ functions is slightly excessive, as the un-managed versions of these functions is a little cleaner (and slightly more economical in terms of allocation). This change converts the devm_regulator_{get,put}() to regulator_{get,put}() in the get_alignment_from_regulator() function of this driver. Signed-off-by: Alexandru Ardelean Link: https://lore.kernel.org/r/20210624084737.42336-1-aardelean@deviqon.com Reviewed-by: Thierry Reding Signed-off-by: Stephen Boyd

clk: tegra: tegra124-emc: Fix clock imbalance in emc_set_timing()

2021-06-02T09:08:00+00:00

After calling clk_prepare_enable(), clk_disable_unprepare() needs be called when prepare_timing_change() failed. Reported-by: Hulk Robot Signed-off-by: Yang Yingliang Signed-off-by: Thierry Reding

clk: tegra: Don't deassert reset on enabling clocks

2021-05-31T13:16:46+00:00

The Tegra clock driver contains legacy code which deasserts hardware reset when peripheral clocks are enabled. This behaviour comes from a pre-CCF era of the Tegra drivers. This is unacceptable for modern kernel drivers which use generic CCF and reset-control APIs because it breaks assumptions of the drivers about clk/reset sequences and about reset-propagation delays. Hence remove the awkward legacy behaviour from the clk driver. In particular PMC driver assumes that hardware blocks remains in reset while power domain is turning on, but the clk driver deasserts the reset before power clamp is removed, hence breaking the driver's assumption. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

clk: tegra: Mark external clocks as not having reset control

2021-05-31T13:16:46+00:00

The external clocks don't have reset bits as they don't belong to any specific hardware unit. Mark them as not having reset control for consistency. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling

2021-05-31T13:16:26+00:00

Check whether thermal DIV2 throttle is active in order to report the CPU frequency properly. This very useful for userspace tools like cpufreq-info which show actual frequency asserted from hardware. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

clk: tegra: Don't allow zero clock rate for PLLs

2021-05-31T13:16:26+00:00

Zero clock rate doesn't make sense for PLLs and tegra-clk driver enters into infinite loop on trying to calculate PLL parameters for zero rate. Make code to error out if requested rate is zero. Originally this trouble was found by Robert Yang while he was trying to bring up upstream kernel on Samsung Galaxy Tab, which happened due to a bug in Tegra DRM driver that erroneously sets PLL rate to zero. This issues came over again recently during of kernel bring up on ASUS TF700T. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding