kernel/linux.git/drivers/clk/tegra, branch v4.4.171

clk: tegra: Fix PLL_U post divider and initial rate on Tegra30

2018-07-25T08:18:32+00:00

commit 797097301860c64b63346d068ba4fe4992bd5021 upstream. The post divider value in the frequency table is wrong as it would lead to the PLL producing an output rate of 960 MHz instead of the desired 480 MHz. This wasn't a problem as nothing used the table to actually initialize the PLL rate, but the bootloader configuration was used unaltered. If the bootloader does not set up the PLL it will fail to come when used under Linux. To fix this don't rely on the bootloader, but set the correct rate in the clock driver. Signed-off-by: Lucas Stach Signed-off-by: Thierry Reding [jonathanh@nvidia.com: Back-ported to stable v4.4.y] Signed-off-by: Jon Hunter Signed-off-by: Greg Kroah-Hartman

clk: tegra: Fix cclk_lp divisor register

2017-12-20T09:04:59+00:00

[ Upstream commit 54eff2264d3e9fd7e3987de1d7eba1d3581c631e ] According to comments in code and common sense, cclk_lp uses its own divisor, not cclk_g's. Fixes: b08e8c0ecc42 ("clk: tegra: add clock support for Tegra30") Signed-off-by: Michał Mirosław Acked-By: Peter De Schrijver Signed-off-by: Thierry Reding Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman

Merge tag 'tegra-for-4.4-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next

2015-10-20T15:49:11+00:00

clk: tegra: Changes for v4.4-rc1 This contains a patch that allows the DFLL to use clock rates higher than 2^31-1 Hz by using the ->determine_rate() operation instead of the ->round_rate() operation. Other than that there's a couple of cleanups in preparation for Tegra210 support.

clk: tegra: Modify tegra_audio_clk_init to accept more plls

2015-10-20T11:56:55+00:00

tegra_audio_clk_init was written expecting a single PLL to be passed in directly. Change this to accept an array which will allow for supporting multiple plls and specifying specific data about them, like their parent, which may change over time. Reviewed-by: Benson Leung Signed-off-by: Rhyland Klein Signed-off-by: Thierry Reding

clk: tegra: Update struct tegra_clk_pll_params kerneldoc

2015-10-20T11:56:55+00:00

Benson Leung pointed out that the kerneldoc for this structure has become stale. Update the field descriptions to match the structure content. Reported-by: Benson Leung Acked-by: Rhyland Klein Signed-off-by: Thierry Reding Reviewed-by: Benson Leung Signed-off-by: Rhyland Klein Signed-off-by: Thierry Reding

clk: tegra: Fix comments for structure definitions

2015-10-20T11:56:55+00:00

Some fields moved from the tegra_clk_pll struct to the tegra_pll_params struct. Update the struct comments to reflect where the fields really are. Signed-off-by: Rhyland Klein Acked-By: Peter De Schrijver Reviewed-by: Benson Leung Signed-off-by: Thierry Reding

clk: tegra: dfll: Monitor code is DEBUG_FS only

2015-10-20T11:56:54+00:00

The monitor code is used with DEBUG_FS only, so move it into the corresponding #ifdef block to avoid potential compiler warnings. Signed-off-by: Thierry Reding

clk: tegra: delete unneeded of_node_put

2015-10-12T18:52:48+00:00

for_each_child_of_node performs an of_node_put on each iteration, so putting an of_node_put before a continue results in a double put. The semantic match that finds this problem is as follows (http://coccinelle.lip6.fr): // @@ expression root,e; local idexpression child; iterator name for_each_child_of_node; @@ for_each_child_of_node(root, child) { ... when != of_node_get(child) * of_node_put(child); ... * continue; } // Signed-off-by: Julia Lawall Signed-off-by: Stephen Boyd

clk: tegra: dfll: Properly protect OPP list

2015-09-16T22:16:03+00:00

The OPP list needs to be protected against concurrent accesses. Using simple RCU read locks does the trick and gets rid of the following lockdep warning: =============================== [ INFO: suspicious RCU usage. ] 4.2.0-next-20150908 #1 Not tainted ------------------------------- drivers/base/power/opp.c:460 Missing rcu_read_lock() or dev_opp_list_lock protection! other info that might help us debug this: rcu_scheduler_active = 1, debug_locks = 0 4 locks held by kworker/u8:0/6: #0: ("%s""deferwq"){++++.+}, at: [] process_one_work+0x118/0x4bc #1: (deferred_probe_work){+.+.+.}, at: [] process_one_work+0x118/0x4bc #2: (&dev->mutex){......}, at: [] __device_attach+0x20/0x118 #3: (prepare_lock){+.+...}, at: [] clk_prepare_lock+0x10/0xf8 stack backtrace: CPU: 2 PID: 6 Comm: kworker/u8:0 Not tainted 4.2.0-next-20150908 #1 Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) Workqueue: deferwq deferred_probe_work_func [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [] (show_stack) from [] (dump_stack+0x94/0xd4) [] (dump_stack) from [] (dev_pm_opp_find_freq_ceil+0x108/0x114) [] (dev_pm_opp_find_freq_ceil) from [] (dfll_calculate_rate_request+0xb8/0x170) [] (dfll_calculate_rate_request) from [] (dfll_clk_round_rate+0x1c/0x2c) [] (dfll_clk_round_rate) from [] (clk_calc_new_rates+0x1b8/0x228) [] (clk_calc_new_rates) from [] (clk_core_set_rate_nolock+0x44/0xac) [] (clk_core_set_rate_nolock) from [] (clk_set_rate+0x24/0x34) [] (clk_set_rate) from [] (tegra124_cpufreq_probe+0x120/0x230) [] (tegra124_cpufreq_probe) from [] (platform_drv_probe+0x44/0xac) [] (platform_drv_probe) from [] (driver_probe_device+0x218/0x304) [] (driver_probe_device) from [] (bus_for_each_drv+0x60/0x94) [] (bus_for_each_drv) from [] (__device_attach+0xb4/0x118) ata1: SATA link down (SStatus 0 SControl 300) [] (__device_attach) from [] (bus_probe_device+0x88/0x90) [] (bus_probe_device) from [] (deferred_probe_work_func+0x58/0x8c) [] (deferred_probe_work_func) from [] (process_one_work+0x188/0x4bc) [] (process_one_work) from [] (worker_thread+0x4c/0x4f4) [] (worker_thread) from [] (kthread+0xe4/0xf8) [] (kthread) from [] (ret_from_fork+0x14/0x24) Signed-off-by: Thierry Reding Fixes: c4fe70ada40f ("clk: tegra: Add closed loop support for the DFLL") [vince.h@nvidia.com: Unlock rcu on error path] Signed-off-by: Vince Hsu [sboyd@codeaurora.org: Dropped second hunk that nested the rcu read lock unnecessarily] Signed-off-by: Stephen Boyd

clk: tegra: Unlock top rates for Tegra124 DFLL clock

2015-09-15T10:54:39+00:00

The new determine_rate prototype allows for clock rates exceeding 2^31-1 Hz to be used. Switch the DFLL clock to use determine_rate instead of round_rate and unlock the top rates supported by the Tegra124. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding