kernel/linux.git/drivers/clk/tegra, branch v4.11.5

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2017-02-25T22:28:06+00:00

Pull clk updates from Stephen Boyd: "The usual collection of new drivers, non-critical fixes, and updates to existing clk drivers. The bulk of the work is on Allwinner and Rockchip SoCs, but there's also an Intel Atom driver in here too. New Drivers: - Tegra BPMP firmware - Hisilicon hi3660 SoCs - Rockchip rk3328 SoCs - Intel Atom PMC - STM32F746 - IDT VersaClock 5P49V5923 and 5P49V5933 - Marvell mv98dx3236 SoCs - Allwinner V3s SoCs Removed Drivers: - Samsung Exynos4415 SoCs Updates: - Migrate ABx500 to OF - Qualcomm IPQ4019 CPU clks and general PLL support - Qualcomm MSM8974 RPM - Rockchip non-critical fixes and clk id additions - Samsung Exynos4412 CPUs - Socionext UniPhier NAND and eMMC support - ZTE zx296718 i2s and other audio clks - Renesas CAN and MSIOF clks for R-Car M3-W - Renesas resets for R-Car Gen2 and Gen3 and RZ/G1 - TI CDCE913, CDCE937, and CDCE949 clk generators - Marvell Armada ap806 CPU frequencies - STM32F4* I2S/SAI support - Broadcom BCM2835 DSI support - Allwinner sun5i and A80 conversion to new style clk bindings" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (130 commits) clk: renesas: mstp: ensure register writes complete clk: qcom: Do not drop device node twice clk: mvebu: adjust clock handling for the CP110 system controller clk: mvebu: Expand mv98dx3236-core-clock support clk: zte: add i2s clocks for zx296718 clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR() clk: sunxi-ng: select SUNXI_CCU_MULT for sun5i clk: sunxi-ng: Check kzalloc() for errors and cleanup error path clk: tegra: Add BPMP clock driver clk: uniphier: add eMMC clock for LD11 and LD20 SoCs clk: uniphier: add NAND clock for all UniPhier SoCs ARM: dts: sun9i: Switch to new clock bindings clk: sunxi-ng: Add A80 Display Engine CCU clk: sunxi-ng: Add A80 USB CCU clk: sunxi-ng: Add A80 CCU clk: sunxi-ng: Support separately grouped PLL lock status register clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers clk: qcom: SDHCI enablement on Nexus 5X / 6P ...

clk: tegra: Add BPMP clock driver

2017-02-03T20:36:36+00:00

This driver uses the services provided by the BPMP firmware driver to implement a clock driver based on the MRQ_CLK request. This part of the BPMP ABI provides a means to enumerate and control clocks and should allow the driver to work on any chip that supports this ABI. Signed-off-by: Thierry Reding Signed-off-by: Stephen Boyd

PM / OPP: Update OPP users to put reference

2017-01-30T08:22:21+00:00

This patch updates dev_pm_opp_find_freq_*() routines to get a reference to the OPPs returned by them. Also updates the users of dev_pm_opp_find_freq_*() routines to call dev_pm_opp_put() after they are done using the OPPs. As it is guaranteed the that OPPs wouldn't get freed while being used, the RCU read side locking present with the users isn't required anymore. Drop it as well. This patch also updates all users of devfreq_recommended_opp() which was returning an OPP received from the OPP core. Note that some of the OPP core routines have gained rcu_read_{lock|unlock}() calls, as those still use RCU specific APIs within them. Signed-off-by: Viresh Kumar Reviewed-by: Chanwoo Choi [Devfreq] Signed-off-by: Rafael J. Wysocki

clk: tegra: dfll: Use builtin_platform_driver to simplify the code

2016-11-10T22:08:46+00:00

Use the builtin_platform_driver() macro to make the code simpler. Signed-off-by: Wei Yongjun Signed-off-by: Stephen Boyd

clk: tegra: make clk-tegra124-dfll-fcpu explicitly non-modular

2016-11-04T20:33:11+00:00

The Kconfig currently controlling compilation of this code is: arch/arm/mach-tegra/Kconfig:config ARCH_TEGRA_124_SOC arch/arm/mach-tegra/Kconfig: bool "Enable support for Tegra124 family" ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tags etc. since all that information is already contained at the top of the file in the comments. Cc: Peter De Schrijver Cc: Prashant Gaikwad Cc: Michael Turquette Cc: Stephen Boyd Cc: Stephen Warren Cc: Thierry Reding Cc: Alexandre Courbot Cc: Aleksandr Frid Cc: Paul Walmsley Cc: linux-clk@vger.kernel.org Cc: linux-tegra@vger.kernel.org Signed-off-by: Paul Gortmaker Signed-off-by: Stephen Boyd

clk: tegra: dfll: improve function-level documentation

2016-11-02T00:38:50+00:00

Adjust variables to correspond to the names used in the parameter list of the function. Move the struct device * variable up to the place where it appears in the parameter list. Issue detected using Coccinelle (http://coccinelle.lip6.fr/) Signed-off-by: Julia Lawall Signed-off-by: Stephen Boyd

clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2

2016-08-24T17:54:17+00:00

Tegra114 has a HW bug that the PLLD/PLLD2 lock bit cannot be asserted when the DIS power domain is during up-powergating process but the clamp to this domain is not removed yet. That causes a timeout and aborts the power sequence, although the PLLD/PLLD2 has already locked. To remove the false alarm, we don't use the lock for PLLD/PLLD2. Just wait 1ms and treat the clocks as locked. Signed-off-by: Vince Hsu Tested-by: Jonathan Hunter Signed-off-by: Thierry Reding Signed-off-by: Stephen Boyd

clk: tegra: Initialize UTMI PLL when enabling PLLU

2016-06-30T15:43:17+00:00

Move the UTMI PLL initialization code form clk-tegra.c files into clk-pll.c. UTMI PLL was being configured and set in HW control right after registration. However, when the clock init_table is processed and child clks of PLLU are enabled, it will call in and enable PLLU as well, and initiate SW enabling sequence even though PLLU is already in HW control. This leads to getting UTMIPLL stuck with a SEQ_BUSY status. Doing the initialization once during pllu_enable means we configure it properly into HW control. A side effect of the commonization/localization of the UTMI PLL init code, is that it corrects some errors that were present for earlier generations. For instance, in clk-tegra124.c, it used to have: #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) when the correct shift to use is present in the new version: #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) which matches the Tegra124 TRM register definition. Signed-off-by: Andrew Bresticker [rklein: Merged in some later fixes for potential deadlocks] Signed-off-by: Rhyland Klein [treding: coding style bike-shedding, remove unused variable] Signed-off-by: Thierry Reding

clk: tegra: Micro-optimize Tegra210 clock setup

2016-06-23T15:47:03+00:00

sor_safe being the parent of the dpaux and dpaux1 clocks, it's not only natural, but also slightly more efficient, to initialize it before its children. This avoids orphaning the dpaux and dpaux1 clocks only to get them reparented when the sor_safe clock is registered. Acked-by: Jon Hunter Tested-by: Jon Hunter Acked-by: Rhyland Klein Signed-off-by: Thierry Reding

clk: tegra: Make sor_safe the parent of dpaux and dpaux1

2016-06-23T15:46:33+00:00

It turns out that sor_safe, rather than pll_p, is the parent of the dpaux and dpaux1 clocks. Acked-by: Jon Hunter Tested-by: Jon Hunter Acked-by: Rhyland Klein Signed-off-by: Thierry Reding