kernel/linux.git/drivers/clk/st, branch v6.18.21

Merge branch 'clk-determine-rate' into clk-next

2025-10-06T18:02:50+00:00

* clk-determine-rate: (120 commits) clk: microchip: core: remove duplicate roclk_determine_rate() clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driver clk: scmi: migrate round_rate() to determine_rate() clk: ti: fapll: convert from round_rate() to determine_rate() clk: ti: dra7-atl: convert from round_rate() to determine_rate() clk: ti: divider: convert from round_rate() to determine_rate() clk: ti: composite: convert from round_rate() to determine_rate() clk: ti: dpll: convert from round_rate() to determine_rate() clk: ti: dpll: change error return from ~0 to -EINVAL clk: ti: dpll: remove round_rate() in favor of determine_rate() clk: tegra: tegra210-emc: convert from round_rate() to determine_rate() clk: tegra: super: convert from round_rate() to determine_rate() clk: tegra: pll: convert from round_rate() to determine_rate() clk: tegra: periph: divider: convert from round_rate() to determine_rate() clk: tegra: divider: convert from round_rate() to determine_rate() clk: tegra: audio-sync: convert from round_rate() to determine_rate() clk: fixed-factor: drop round_rate() clk ops clk: divider: remove round_rate() in favor of determine_rate() clk: visconti: pll: convert from round_rate() to determine_rate() clk: versatile: vexpress-osc: convert from round_rate() to determine_rate() ...

clk: st: flexgen: remove unused compatible

2025-09-21T16:52:29+00:00

Following B2120 boards removal in commit dee546e1adef ("ARM: sti: drop B2120 board support"), several compatibles are left unused. Remove them. Signed-off-by: Raphael Gallais-Pou Reviewed-by: Patrice Chotard Reviewed-by: Brian Masney Signed-off-by: Stephen Boyd

clk: st: clkgen-pll: convert from round_rate() to determine_rate()

2025-09-08T13:41:28+00:00

The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Note that prior to running the Coccinelle: - round_rate_stm_pll4600c28() was renamed to stm_pll4600c28_round_rate() - round_rate_stm_pll3200c32() was renamed to stm_pll3200c32_round_rate() Signed-off-by: Brian Masney

clk: st: clkgen-fsyn: convert from round_rate() to determine_rate()

2025-09-08T13:41:28+00:00

The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney

clk: st: flexgen: Switch to determine_rate

2023-06-09T01:39:35+00:00

The ST Flexgen clocks implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The driver does implement round_rate() though, which means that we can change the rate of the clock, but we will never get to change the parent. However, It's hard to tell whether it's been done on purpose or not. Since we'll start mandating a determine_rate() implementation, let's convert the round_rate() implementation to a determine_rate(), which will also make the current behavior explicit. And if it was an oversight, the clock behaviour can be adjusted later on. Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-62-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd

clk: st: Fix memory leak in st_of_quadfs_setup()

2022-12-08T02:27:11+00:00

If st_clk_register_quadfs_pll() fails, @lock should be freed before goto @err_exit, otherwise will cause meory leak issue, fix it. Signed-off-by: Xiu Jianfeng Link: https://lore.kernel.org/r/20221122133614.184910-1-xiujianfeng@huawei.com Reviewed-by: Patrice Chotard Signed-off-by: Stephen Boyd

clk: st: Hold reference returned by of_get_parent()

2022-08-19T21:34:44+00:00

We should hold the reference returned by of_get_parent() and use it to call of_node_put() for refcount balance. Fixes: 3efe64ef5186 ("clk: st: clkgen-fsyn: search reg within node or parent") Fixes: 810251b0d36a ("clk: st: clkgen-mux: search reg within node or parent") Signed-off-by: Liang He Link: https://lore.kernel.org/r/20220628142416.169808-1-windhl@126.com Signed-off-by: Stephen Boyd

clk: st: clkgen-mux: search reg within node or parent

2022-01-06T01:21:28+00:00

In order to avoid having duplicated addresses within the DT, only have one unit-address per clockgen and each driver within the clockgen should look at the parent node (overall clockgen) to figure out the reg property. Such behavior is already in place in other STi platform clock drivers such as clk-flexgen and clkgen-pll. Keep backward compatibility by first looking at reg within the node before looking into the parent node. Signed-off-by: Alain Volmat Link: https://lore.kernel.org/r/20211218211157.188214-3-avolmat@me.com Reviewed-by: Patrice Chotard Signed-off-by: Stephen Boyd

clk: st: clkgen-fsyn: search reg within node or parent

2022-01-06T01:21:28+00:00

In order to avoid having duplicated addresses within the DT, only have one unit-address per clockgen and each driver within the clockgen should look at the parent node (overall clockgen) to figure out the reg property. Such behavior is already in place in other STi platform clock drivers such as clk-flexgen and clkgen-pll. Keep backward compatibility by first looking at reg within the node before looking into the parent node. Signed-off-by: Alain Volmat Link: https://lore.kernel.org/r/20211218211157.188214-2-avolmat@me.com Reviewed-by: Patrice Chotard Signed-off-by: Stephen Boyd

clk: st: clkgen-fsyn: embed soc clock outputs within compatible data

2021-06-28T02:53:40+00:00

In order to avoid relying on the old style description via the DT clock-output-names, add compatible data describing the flexgen outputs clocks for all STiH407/STiH410 and STiH418 SOCs. In order to ease transition between the two methods, this commit introduce the new compatible without removing the old method. Once DTs will be fixed, the method relying on DT clock-output-names will be removed from this driver as well as old compatibles. Signed-off-by: Alain Volmat Reviewed-by: Patrice Chotard Link: https://lore.kernel.org/r/20210331201632.24530-7-avolmat@me.com Signed-off-by: Stephen Boyd