kernel/linux.git/drivers/clk/st, branch v4.8.16

clk: st: clkgen-pll: Detect critical clocks

2016-06-30T19:17:11+00:00

Utilise the new Critical Clock infrastructure to mark clocks which much not be disabled as CRITICAL. Clocks are marked as CRITICAL using clk flags. This patch also ensures flags are peculated through the framework in the correct manner. Signed-off-by: Lee Jones Signed-off-by: Stephen Boyd

clk: st: clkgen-fsyn: Detect critical clocks

2016-06-30T19:17:09+00:00

clk: st: clk-flexgen: Detect critical clocks

2016-06-30T19:17:06+00:00

Utilise the new Critical Clock infrastructure to mark clocks which much not be disabled as CRITICAL. While we're at it, reduce the coverage of the flex_flags variable, since it's only really used in a single for() loop. Signed-off-by: Lee Jones Signed-off-by: Stephen Boyd

clk: st: Remove impossible check for of_clk_get_parent_count() < 0

2016-02-27T00:01:32+00:00

The checks for < 0 are impossible now that of_clk_get_parent_count() returns an unsigned int. Simplify the code and update the types. Cc: Gabriel Fernandez Signed-off-by: Stephen Boyd

clk: st: avoid uninitialized variable use

2016-01-30T01:20:08+00:00

My previous patch fixed some warnings about printing a couple of variables that are always uninitialized in quadfs_pll_fs660c32_set_rate(), but I now got a warning that only shows up in some configurations (i.e. without gcc -Os) about the params.ndiv being used uninitialized in the error case: drivers/clk/st/clkgen-fsyn.c: In function 'quadfs_pll_fs660c32_set_rate': drivers/clk/st/clkgen-fsyn.c:584:75: warning: 'params.ndiv' may be used uninitialized in this function [-Wmaybe-uninitialized] drivers/clk/st/clkgen-fsyn.c:574:16: note: 'params.ndiv' was declared here This changes the error handling so we bail for invalid arguments rather than continuing with uninitialized data. Signed-off-by: Arnd Bergmann Signed-off-by: Stephen Boyd

clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h

2016-01-29T20:59:50+00:00

to_clk_*(_hw) macros have been repeatedly defined in many places. This patch moves all the to_clk_*(_hw) definitions in the common clock framework to public header clk-provider.h, and drop the local definitions. Signed-off-by: Geliang Tang Signed-off-by: Stephen Boyd

clk: st: avoid uninitialized variable use

2015-11-20T18:59:26+00:00

quadfs_pll_fs660c32_round_rate prints a few structure members that are never initialized, and also doesn't print the only one it cares about. We get a gcc warning about the ones that are printed: clk/st/clkgen-fsyn.c:560:93: warning: 'params.sdiv' may be used uninitialized in this function clk/st/clkgen-fsyn.c:560:93: warning: 'params.mdiv' may be used uninitialized in this function clk/st/clkgen-fsyn.c:560:93: warning: 'params.pe' may be used uninitialized in this function clk/st/clkgen-fsyn.c:560:93: warning: 'params.nsdiv' may be used uninitialized in this function This changes the code to no longer print uninitialized data, and for good measure it also prints the ndiv member that is being set. Signed-off-by: Arnd Bergmann Fixes: 5f7aa9071e93 ("clk: st: Support for QUADFS inside ClockGenB/C/D/E/F") Acked-by: Gabriel Fernandez Signed-off-by: Stephen Boyd

drivers: clk: st: Correct the pll-type for A9 for stih418

2015-10-09T06:52:59+00:00

Add support for new PLL-type for stih418 A9-PLL. Currently the 407_A9_PLL type being used, it is corrected with this patch 4600c28 PLL allows to reach higher frequencies so its programming algorithm is extended. Signed-off-by: Pankaj Dev Signed-off-by: Gabriel Fernandez Signed-off-by: Stephen Boyd

drivers: clk: st: PLL rate change implementation for DVFS

2015-10-09T06:52:58+00:00

Change A9 PLL rate, as per requirement from the cpufreq framework, for DVFS. For rate change, the A9 clock needs to be temporarily sourced from PLL external to A9 and then sourced back to A9-PLL Signed-off-by: Pankaj Dev Signed-off-by: Gabriel Fernandez Signed-off-by: Stephen Boyd

drivers: clk: st: Support for enable/disable in Clockgen PLLs

2015-10-09T06:52:57+00:00

The patch adds support for enable/disable of the Clockgen PLLs. clkgen_pll_enable/clkgen_pll_disable added as generic function for all PLLs. Signed-off-by: Pankaj Dev Signed-off-by: Gabriel Fernandez Signed-off-by: Stephen Boyd