<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/clk/samsung/Makefile, branch linux-7.0.y</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=linux-7.0.y</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=linux-7.0.y'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2025-10-20T06:50:35+00:00</updated>
<entry>
<title>clk: samsung: add Exynos ACPM clock driver</title>
<updated>2025-10-20T06:50:35+00:00</updated>
<author>
<name>Tudor Ambarus</name>
<email>tudor.ambarus@linaro.org</email>
</author>
<published>2025-10-10T12:46:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=40498a74205371400a5b0088acb886ac47a523aa'/>
<id>urn:sha1:40498a74205371400a5b0088acb886ac47a523aa</id>
<content type='text'>
Add the Exynos ACPM clock driver. It provides support for clocks that
are controlled by firmware that implements the ACPM interface.

Signed-off-by: Tudor Ambarus &lt;tudor.ambarus@linaro.org&gt;
Reviewed-by: Peter Griffin &lt;peter.griffin@linaro.org&gt;
Tested-by: Peter Griffin &lt;peter.griffin@linaro.org&gt; # on gs101-oriole
Link: https://patch.msgid.link/20251010-acpm-clk-v6-4-321ee8826fd4@linaro.org
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC</title>
<updated>2025-08-31T13:22:33+00:00</updated>
<author>
<name>Hakyeong Kim</name>
<email>hgkim05@coasia.com</email>
</author>
<published>2025-08-25T11:44:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=bd5336e3f7040f300b01702215b45e6267a400cc'/>
<id>urn:sha1:bd5336e3f7040f300b01702215b45e6267a400cc</id>
<content type='text'>
Add initial clock support for Axis ARTPEC-8 SoC which is required
for enabling basic clock management.

Add clock support for below CMU (Clock Management Unit) blocks
in ARTPEC-8 SoC:
 - CMU_CMU
 - CMU_BUS
 - CMU_CORE
 - CMU_CPUCL
 - CMU_FSYS
 - CMU_IMEM
 - CMU_PERI

Signed-off-by: Hakyeong Kim &lt;hgkim05@coasia.com&gt;
Signed-off-by: Varada Pavani &lt;v.pavani@samsung.com&gt;
Signed-off-by: SeonGu Kang &lt;ksk4725@coasia.com&gt;
Signed-off-by: Ravi Patel &lt;ravi.patel@samsung.com&gt;
Link: https://lore.kernel.org/r/20250825114436.46882-4-ravi.patel@samsung.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk: samsung: add initial exynos7870 clock driver</title>
<updated>2025-03-01T14:11:11+00:00</updated>
<author>
<name>Kaustabh Chakraborty</name>
<email>kauschluss@disroot.org</email>
</author>
<published>2025-03-01T03:57:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=4149066a5e958963f7123be51d3a65d336045c21'/>
<id>urn:sha1:4149066a5e958963f7123be51d3a65d336045c21</id>
<content type='text'>
This is a basic implementation of the clock driver required by
Samsung's Exynos7870 SoC. It implements CMU_MIF, CMU_DISPAUD, CMU_FSYS,
CMU_G3D, CMU_ISP, CMU_MFCMSCL, and CMU_PERI. all other CMUs depend on
CMU_MIF.

Signed-off-by: Kaustabh Chakraborty &lt;kauschluss@disroot.org&gt;
Link: https://lore.kernel.org/r/20250301-exynos7870-pmu-clocks-v5-2-715b646d5206@disroot.org
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk: samsung: introduce Exynos2200 clock driver</title>
<updated>2025-03-01T14:08:11+00:00</updated>
<author>
<name>Ivaylo Ivanov</name>
<email>ivo.ivanov.ivanov1@gmail.com</email>
</author>
<published>2025-02-23T11:56:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=11fd259b7a9c386179f4bb9657c7597c8e8de067'/>
<id>urn:sha1:11fd259b7a9c386179f4bb9657c7597c8e8de067</id>
<content type='text'>
CMU_TOP is the top level clock management unit which contains PLLs,
muxes, dividers and gates that feed the other clock management units.

CMU_ALIVE provides clocks for SPMI, the new MCT and other clock
management units

CMU_CMGP provides clocks for USI blocks
CMU_HSI0 provides clocks for USB
CMU_PERIC0 provides clocks for USI4 and I3C blocks
CMU_PERIC1 provides clocks for USI blocks
CMU_PERIC2 provides clocks for USI and I3C blocks
CMU_PERIS provides clocks for GIC and the legacy MCT
CMU_UFS provides clocks for UFS
CMU_VTS provides clocks for other clock management units
like CMU_AUD, which will be added in the future.

Signed-off-by: Ivaylo Ivanov &lt;ivo.ivanov.ivanov1@gmail.com&gt;
Link: https://lore.kernel.org/r/20250223115601.723886-4-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk: samsung: Introduce Exynos990 clock controller driver</title>
<updated>2024-12-14T10:39:02+00:00</updated>
<author>
<name>Igor Belwon</name>
<email>igor.belwon@mentallysanemainliners.org</email>
</author>
<published>2024-12-09T14:45:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=bdd03ebf721f70df1458a720b25998a489f63297'/>
<id>urn:sha1:bdd03ebf721f70df1458a720b25998a489f63297</id>
<content type='text'>
The current implementation contains support for:
- CMU_TOP - which generates clocks for other blocks
- CMU_HSI0 - which generates clocks for USB31.

Signed-off-by: Igor Belwon &lt;igor.belwon@mentallysanemainliners.org&gt;
Link: https://lore.kernel.org/r/20241209-exynos990-cmu-v4-3-57f07080f9e4@mentallysanemainliners.org
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk: samsung: Introduce Exynos8895 clock driver</title>
<updated>2024-10-26T12:00:12+00:00</updated>
<author>
<name>Ivaylo Ivanov</name>
<email>ivo.ivanov.ivanov1@gmail.com</email>
</author>
<published>2024-10-23T09:01:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9174fac3b302a853b78c78f2f5ad11462b0c54b0'/>
<id>urn:sha1:9174fac3b302a853b78c78f2f5ad11462b0c54b0</id>
<content type='text'>
CMU_TOP is the top level clock management unit which contains PLLs, muxes,
dividers and gates that feed the other clock management units.

CMU_PERIS provides clocks for GIC and MCT
CMU_FSYS0 provides clocks for USBDRD30
CMU_FSYS1 provides clocks for MMC, UFS and PCIE
CMU_PERIC0 provides clocks for UART_DBG, USI00 ~ USI03
CMU_PERIC1 provides clocks for SPI_CAM0/1, UART_BT, USI04 ~ USI13,
HSI2C_CAM0/1/2/3

Signed-off-by: Ivaylo Ivanov &lt;ivo.ivanov.ivanov1@gmail.com&gt;
Link: https://lore.kernel.org/r/20241023090136.537395-4-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk: samsung: add top clock support for ExynosAuto v920 SoC</title>
<updated>2024-08-23T07:21:35+00:00</updated>
<author>
<name>Sunyeal Hong</name>
<email>sunyeal.hong@samsung.com</email>
</author>
<published>2024-08-21T23:26:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=485e13fe2fb649e60eb49d8bec4404da215c1f5b'/>
<id>urn:sha1:485e13fe2fb649e60eb49d8bec4404da215c1f5b</id>
<content type='text'>
This adds support for CMU_TOP which generates clocks for all the
function blocks such as CORE, HSI0/1/2, PERIC0/1 and so on. For
CMU_TOP, PLL_SHARED0,1,2,3,4 and 5 will be the sources of this block
and they will generate bus clocks.

Signed-off-by: Sunyeal Hong &lt;sunyeal.hong@samsung.com&gt;
Link: https://lore.kernel.org/r/20240821232652.1077701-5-sunyeal.hong@samsung.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk: samsung: clk-gs101: Add cmu_top, cmu_misc and cmu_apm support</title>
<updated>2023-12-12T19:29:03+00:00</updated>
<author>
<name>Peter Griffin</name>
<email>peter.griffin@linaro.org</email>
</author>
<published>2023-12-11T16:23:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=2c597bb7d66a55f2af2fff9bf4629dd07b3b9a1e'/>
<id>urn:sha1:2c597bb7d66a55f2af2fff9bf4629dd07b3b9a1e</id>
<content type='text'>
cmu_top is the top level clock management unit which contains PLLs, muxes,
dividers and gates that feed the other clock management units.

cmu_misc clocks IPs such as Watchdog and cmu_apm clocks ips part of the
APM module.

Reviewed-by: Sam Protsenko &lt;semen.protsenko@linaro.org&gt;
Reviewed-by: André Draszik &lt;andre.draszik@linaro.org&gt;
Acked-by: Chanwoo Choi &lt;cw00.choi@samsung.com&gt;
Tested-by: Will McVicker &lt;willmcvicker@google.com&gt;
Signed-off-by: Peter Griffin &lt;peter.griffin@linaro.org&gt;
Link: https://lore.kernel.org/r/20231211162331.435900-9-peter.griffin@linaro.org
[krzysztof: drop not needed linux/of_device.h include]
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk: remove s3c24xx driver</title>
<updated>2023-01-16T08:26:06+00:00</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2022-09-30T11:11:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=594b3caeaf7938ce49a920b8fc835a67216ada28'/>
<id>urn:sha1:594b3caeaf7938ce49a920b8fc835a67216ada28</id>
<content type='text'>
The s3c24xx platform is gone, so the clk driver can be removed as
well.

Acked-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>clk: samsung: add top clock support for Exynos Auto v9 SoC</title>
<updated>2022-05-10T17:19:34+00:00</updated>
<author>
<name>Chanho Park</name>
<email>chanho61.park@samsung.com</email>
</author>
<published>2022-05-04T07:51:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6587c62f69dc11ca80ca746854626bf0394e1088'/>
<id>urn:sha1:6587c62f69dc11ca80ca746854626bf0394e1088</id>
<content type='text'>
This adds support for CMU_TOP which generates clocks for all the
function blocks such as CORE, FSYS0/1/2, PERIC0/1 and so on. For
CMU_TOP, PLL_SHARED0,1,2,3 and 4 will be the sources of this block
and they will generate bus clocks.

Signed-off-by: Chanho Park &lt;chanho61.park@samsung.com&gt;
Signed-off-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Acked-by: Chanwoo Choi &lt;cw00.choi@samsung.com&gt;
Link: https://lore.kernel.org/r/20220504075154.58819-4-chanho61.park@samsung.com
</content>
</entry>
</feed>
