kernel/linux.git/drivers/clk/rockchip, branch linux-5.11.y

clk: rockchip: fix i2s gate bits on rk3066 and rk3188

2020-11-29T19:10:45+00:00

The Rockchip PX2/RK3066 uses these bits in CRU_CLKGATE7_CON: hclk_i2s_8ch_gate_en bit 4 (dtsi: i2s0) hclk_i2s0_2ch_gate_en bit 2 (dtsi: i2s1) hclk_i2s1_2ch_gate_en bit 3 (dtsi: i2s2) The Rockchip PX3/RK3188 uses this bit in CRU_CLKGATE7_CON: hclk_i2s_2ch_gate_en bit 2 (dtsi: i2s0) The bits got somehow mixed up in the clk-rk3188.c file. The labels in the dtsi files are not suppose to change. The sclk and hclk names should match for "trace_event=clk_disable,clk_enable", so remove GATE HCLK_I2S0 from the common clock tree and fix the bits in the rk3066 and rk3188 clock tree. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20201118135822.9582-3-jbx6244@gmail.com Signed-off-by: Heiko Stuebner

clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks

2020-11-29T19:10:44+00:00

Add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks, so that the parent COMPOSITE_FRACMUX and COMPOSITE_NOMUX also update. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20201118135822.9582-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner

clk: rockchip: Remove redundant null check before clk_prepare_enable

2020-11-29T19:02:58+00:00

Because clk_prepare_enable() already checked NULL clock parameter, so the additional check is unnecessary, just remove it. Signed-off-by: Xu Wang Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20201127090551.50254-1-vulab@iscas.ac.cn Signed-off-by: Heiko Stuebner

clk: rockchip: Add appropriate arch dependencies

2020-10-26T11:24:56+00:00

There's no point offering support for 32-bit platforms to users configuring a 64-bit kernel - and vice-versa - unless they are explicitly interested in compile-testing. Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/72abb0f794b8ed77e274e8ee21c22e0bd3223dfd.1603710913.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2020-10-22T19:53:28+00:00

Pull clk updates from Stephen Boyd: "This contains no changes to the core framework. It is a collection of various clk driver updates. The biggest driver updates in terms of lines of code is the Allwinner driver, closely followed by the Qualcomm and Mediatek drivers. All of those hit high because we add so many lines of clk data. Coming in fourth place is i.MX which also adds a bunch of clk data. This accounts for the new driver additions this time around. Otherwise the patches are lots of little cleanups and fixes for various clk drivers that have baked in linux-next for a while. I suppose one highlight or theme is that more clk drivers are being updated to work as modules, which is interesting to see such critical SoC infrastructure work as a loadable module. New Drivers: - Support qcom SM8150/SM8250 video and display clks - Support Mediatek MT8167 clks - Add clock for CRC block found on vf610 SoCs - Add support for the Renesas R-Car V3U (R8A779A0) SoC - Add support for the VSP for Resizing clock on Renesas RZ/G1H - Support Allwinner A100 SoC clks Removed Drivers: - Remove i.MX21 clock driver, as i.MX21 platform support is being dropped Updates: - Change how qcom's display port clks work - Small non-critical fixes for TI clk driver - Remove various unused variables in clk drivers - Allow Rockchip clk driver to be a module - Remove most __clk_lookup() calls in Samsung drivers (yay!) - Support building i.MX ARMv8 platforms clock driver as module - Some kerneldoc fixes here and there - A couple of minor i.MX clk data corrections - Update audio clock inverter and fdiv2 flag on Amlogic g12 - Make amlogic clk drivers configurable in Kconfig - Fix Renesas VSP clock names to match corrected hardware documentation - Sigma-delta modulation on Allwinner R40 - Various fixes for at91 clk driver - Use semicolons instead of commas in some places - Mark some variables const so they can move to RO memory" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (102 commits) clk: imx8mq: Fix usdhc parents order clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on clk: Restrict CLK_HSDK to ARC_SOC_HSDK clk: at91: sam9x60: support only two programmable clocks clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL clk: ingenic: Use readl_poll_timeout instead of custom loop clk: ingenic: Use to_clk_info() macro for all clocks clk: bcm2835: add missing release if devm_clk_hw_register fails clk: at91: clk-sam9x60-pll: remove unused variable clk: at91: clk-main: update key before writing AT91_CKGR_MOR clk: at91: remove the checking of parent_name clk: clk-prima2: fix return value check in prima2_clk_init() clk: mmp2: Fix the display clock divider base clk: pxa: Constify static struct clk_ops clk: baikal-t1: Mark Ethernet PLL as critical clk: qoriq: modify MAX_PLL_DIV to 32 clk: axi-clkgen: Set power bits for fractional mode clk: axi-clkgen: Add support for fractional dividers ...

clk: rockchip: Initialize hw to error to avoid undefined behavior

2020-10-08T02:08:38+00:00

We can get down to this return value from ERR_CAST() without initializing hw. Set it to -ENOMEM so that we always return something sane. Fixes the following smatch warning: drivers/clk/rockchip/clk-half-divider.c:228 rockchip_clk_register_halfdiv() error: uninitialized symbol 'hw'. drivers/clk/rockchip/clk-half-divider.c:228 rockchip_clk_register_halfdiv() warn: passing zero to 'ERR_CAST' Cc: Elaine Zhang Cc: Heiko Stuebner Fixes: 956060a52795 ("clk: rockchip: add support for half divider") Reviewed-by: Heiko Stuebner Signed-off-by: Stephen Boyd

clk: rockchip: rk3399: Support module build

2020-09-22T13:16:54+00:00

support CLK_OF_DECLARE and builtin_platform_driver_probe double clk init method. add module author, description and license to support building Soc Rk3399 clock driver as module. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20200914022316.24045-1-zhangqing@rock-chips.com Signed-off-by: Heiko Stuebner

clk: rockchip: fix the clk config to support module build

2020-09-22T13:16:38+00:00

use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers. use CONFIG_CLK_RKXX for Rk soc clk driver. Mark CONFIG_CLK_RK3399 to "tristate", to support building Rk3399 SoC clock driver as module. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20200914022304.23908-1-zhangqing@rock-chips.com Signed-off-by: Heiko Stuebner

clk: rockchip: Export some clock common APIs for module drivers

2020-09-22T13:16:38+00:00

This is used by the Rockchip clk driver, export it to allow that driver to be compiled as a module. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20200914022225.23613-5-zhangqing@rock-chips.com Signed-off-by: Heiko Stuebner

clk: rockchip: Export rockchip_register_softrst()

2020-09-22T13:16:38+00:00

This is used by the Rockchip clk driver, export it to allow that driver to be compiled as a module.. Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20200914022225.23613-4-zhangqing@rock-chips.com Signed-off-by: Heiko Stuebner