kernel/linux.git/drivers/clk/rockchip/Makefile, branch linux-7.0.y

clk: rockchip: Add clock and reset driver for RK3506

2025-11-23T21:56:49+00:00

Add the clock and reset tree definitions for the new RK3506 SoC. Signed-off-by: Finley Xiao Signed-off-by: Elaine Zhang Link: https://patch.msgid.link/20251121075350.2564860-3-zhangqing@rock-chips.com Signed-off-by: Heiko Stuebner

clk: rockchip: Add clock controller for the RV1126B

2025-11-20T19:57:42+00:00

Add the clock and reset tree definitions for the new rv1126b SoC. Signed-off-by: Elaine Zhang Link: https://patch.msgid.link/20251111025738.869847-4-zhangqing@rock-chips.com Signed-off-by: Heiko Stuebner

clk: rockchip: rename gate-grf clk file

2025-05-13T18:30:15+00:00

All Rockchip clock types live in files starting with clk-foo, so rename the newly added gate-grf-clock to follow that scheme. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250508182752.1925313-3-heiko@sntech.de

clk: rockchip: introduce GRF gates

2025-05-05T20:39:24+00:00

Some rockchip SoCs, namely the RK3576, have bits in a General Register File (GRF) that act just like clock gates. The downstream vendor kernel simply maps over the already mapped GRF range with a generic clock gate driver. This solution isn't suitable for upstream, as a memory range will be in use by multiple drivers at the same time, and it leaks implementation details into the device tree. Instead, implement this with a new clock branch type in the Rockchip clock driver: GRF gates. Somewhat akin to MUXGRF, this clock branch depends on the type of GRF, but functions like a gate instead. Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20250502-rk3576-sai-v3-3-376cef19dd7c@collabora.com Signed-off-by: Heiko Stuebner

clk: rockchip: Add clock controller for the RK3562

2025-03-02T16:51:51+00:00

Add the clock tree definition for the new RK3562 SoC. Signed-off-by: Finley Xiao Signed-off-by: Tao Huang Signed-off-by: Sugar Zhang Signed-off-by: Kever Yang Link: https://lore.kernel.org/r/20250227105916.2340856-3-kever.yang@rock-chips.com [dropped non-working module code, cleaned up init a bit to address build failure reported from kernel test robot Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202503021302.FjsycBI2-lkp@intel.com/ ] Signed-off-by: Heiko Stuebner

clk: rockchip: rk3528: Add reset lookup table

2025-02-27T19:08:25+00:00

In the commit 5d0eb375e685 ("clk: rockchip: Add clock controller driver for RK3528 SoC") only the dt-binding header was added for the reset controller for the RK3528 SoC. Add a reset lookup table generated from the SRST symbols used by vendor linux-6.1-stan-rkr5 kernel to complete support for the reset controller. Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20250227175302.2950788-1-jonas@kwiboo.se Signed-off-by: Heiko Stuebner

clk: rockchip: Add clock controller driver for RK3528 SoC

2025-02-26T17:04:29+00:00

Add clock tree definition for RK3528. Similar to previous Rockchip SoCs, clock controller of RK3528 is combined with the reset controller. We omit the reset part for now since it's hard to test it without support for other basic peripherals. Signed-off-by: Yao Zi Link: https://lore.kernel.org/r/20250217061142.38480-8-ziyao@disroot.org Signed-off-by: Heiko Stuebner

clk: rockchip: implement linked gate clock support

2025-01-09T15:19:21+00:00

Recent Rockchip SoCs have a new hardware block called Native Interface Unit (NIU), which gates clocks to devices behind them. These clock gates will only have a running output clock when all of the following conditions are met: 1. the parent clock is enabled 2. the enable bit is set correctly 3. the linked clock is enabled To handle them this code registers them as a normal gate type clock, which takes care of condition 1 + 2. The linked clock is handled by using runtime PM clocks. Handling it via runtime PM requires setting up a struct device for each of these clocks with a driver attached to use the correct runtime PM operations. Thus the complete handling of these clocks has been moved into its own driver. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20241211165957.94922-5-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner

clk: rockchip: Add clock controller for the RK3576

2024-08-29T09:13:33+00:00

Add the clock and reset tree definitions for the new RK3576 SoC. As opposed to the other rockchip CRU drivers, the GRF node is looked up via compatible instead of a phandle, which simplifies the device tree bindings. Signed-off-by: Elaine Zhang Signed-off-by: Finley Xiao Signed-off-by: YouMin Chen Signed-off-by: Liang Chen Signed-off-by: Sugar Zhang Signed-off-by: Detlev Casanova Reviewed-by: Elaine Zhang Tested-by: Shawn Lin Acked-by: Dragan Simic Link: https://lore.kernel.org/r/0102019199a7781a-888440f0-a3f7-4a7d-a831-491260cbdfe7-000000@eu-west-1.amazonses.com [dropped additional blank line at EOF in rst-rk3576.c dropped the whole (non-)working as module part] Signed-off-by: Heiko Stuebner

clk: rockchip: add clock controller for the RK3588

2022-11-15T10:37:41+00:00

Add full clock controller support RK3588. [rebase, integrate fixes from Wyon and Finley, add missing frequencies to PLL lookup table, update commit message, add GATE_LINK clocks which downstream handles in its own driver with one DT node per clock] Signed-off-by: Wyon Bi Signed-off-by: Finley Xiao Signed-off-by: Elaine Zhang Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20221018151407.63395-10-sebastian.reichel@collabora.com [dropped module stuff after talking to Sebastian] Signed-off-by: Heiko Stuebner