kernel/linux.git/drivers/clk/qcom, branch v4.4.171

clk: qcom: msm8916: fix mnd_width for codec_digcodec

2018-03-22T08:23:28+00:00

[ Upstream commit d8e488e8242ecf129eebc440c92d800a99ca109d ] This patch fixes missing mnd_width for codec_digital clk, this is now set to 8 inline with datasheet. Fixes: 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support") Signed-off-by: Srinivas Kandagatla Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman

clk: qcom: msm8916: Fix crypto clock flags

2016-06-01T19:15:49+00:00

commit 2a0974aa1a0b40a92387ea03dbfeacfbc9ba182c upstream. This patch adds the CLK_SET_RATE_PARENT flag for the crypto core and ahb blocks. Without this flag, clk_set_rate can fail for certain frequency requests. Signed-off-by: Andy Gross Fixes: 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support") Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

clk: qcom: msm8960: Fix ce3_src register offset

2016-05-11T09:21:12+00:00

commit 0f75e1a370fd843c9e508fc1ccf0662833034827 upstream. The offset seems to have been copied from the sata clk. Fix it so that enabling the crypto engine source clk works. Tested-by: Srinivas Kandagatla Tested-by: Bjorn Andersson Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control") Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

clk: qcom: msm8960: fix ce3_core clk enable register

2016-05-11T09:21:12+00:00

commit 732d6913691848db9fabaa6a25b4d6fad10ddccf upstream. This patch corrects the enable register offset which is actually 0x36cc instead of 0x36c4 Signed-off-by: Srinivas Kandagatla Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control") Signed-off-by: Stephen Boyd Signed-off-by: Greg Kroah-Hartman

clk: qcom: msm8960: Fix dsi1/2 halt bits

2015-10-27T20:10:13+00:00

The halt bits for these clocks seem wrong. I get the following warning while booting on an msm8960-cdp: WARNING: CPU: 0 PID: 1 at drivers/clk/qcom/clk-branch.c:97 clk_branch_toggle+0xd0/0x138() dsi1_clk status stuck at 'on' Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.3.0-rc3-00113-g5532cfb567fe #110 Hardware name: Qualcomm (Flattened Device Tree) [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [] (show_stack) from [] (dump_stack+0x70/0xbc) [] (dump_stack) from [] (warn_slowpath_common+0x78/0xb4) [] (warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40) [] (warn_slowpath_fmt) from [] (clk_branch_toggle+0xd0/0x138) [] (clk_branch_toggle) from [] (clk_disable_unused_subtree+0x98/0x1b0) [] (clk_disable_unused_subtree) from [] (clk_disable_unused_subtree+0x20/0x1b0) [] (clk_disable_unused_subtree) from [] (clk_disable_unused+0x58/0xd8) [] (clk_disable_unused) from [] (do_one_initcall+0xac/0x1ec) [] (do_one_initcall) from [] (kernel_init_freeable+0x11c/0x1e8) [] (kernel_init_freeable) from [] (kernel_init+0x8/0xec) [] (kernel_init) from [] (ret_from_fork+0x14/0x3c) Fix the status bits and the errors go away. Fixes: 5532cfb567fe ("clk: qcom: mmcc-8960: Add DSI related clocks") Acked-by: Archit Taneja Signed-off-by: Stephen Boyd

clk: qcom: mmcc-8960: Add DSI related clocks

2015-10-16T22:08:43+00:00

Add rcg and branch clk structs for DSI1 and DSI2 blocks found in MSM8960 and APQ8064. Each DSI instance has 4 pairs of rcg and branch clocks. Populate arrays mmcc_msm8960_clks and mmcc_apq8064_clks with these clocks. Signed-off-by: Archit Taneja Signed-off-by: Stephen Boyd

clk: qcom: clk-rcg: Add customized clk_ops for DSI RCGs

2015-10-16T22:08:40+00:00

DSI specific RCG clocks required customized clk_ops. There are a total of 4 RCGs per DSI block: DSI, BYTE, ESC and PIXEL. There are a total of 2 clocks coming from the DSI PLL, which serve as inputs to these RCGs. The BYTE and ESC RCGs are fed by one of the post dividers of DSI1 or DSI2 PLLs, and the DSI and PIXEL RCGs are fed by another divider of the PLL. In each of the 2 groups above, only one of the clocks sets its parent. These are BYTE RCG and DSI RCG for each of the groups respectively, as shown in the diagram below. The DSI and BYTE RCGs serve as bypass clocks. We create a new set of ops clk_rcg_bypass2_ops, which are like the regular bypass ops, but don't take in a freq table, since the DSI driver using these clocks is parent-able. The PIXEL RCG needs to derive the required pixel clock using dsixpll. It parses a m/n frac table to retrieve the correct clock. The ESC RCG doesn't have a frac M/N block, it can just apply a pre- divider. Its ops simply check if the required clock rate can be achieved by the pre-divider. +-------------------+ | |---dsixpllbyte---o---> To byte RCG | | | (sets parent rate) | | | | | | | DSI 1/2 PLL | | | | o---> To esc RCG | | (doesn't set parent rate) | | | |----dsixpll-----o---> To dsi RCG +-------------------+ | (sets parent rate) ( x = 1, 2 ) | | o---> To pixel rcg (doesn't set parent rate) Signed-off-by: Archit Taneja Signed-off-by: Stephen Boyd

clk: qcom: create virtual child device for TSENS

2015-10-09T06:53:03+00:00

8960 family of devices have TSENS as part of GCC in hardware. Hence DT would represent a GCC node with GCC properties as well as TSENS. Create a virtual platform child device here for TSENS so the driver can probe it and use the parent (GCC) to extract DT properties. Suggested-by: Stephen Boyd Signed-off-by: Rajendra Nayak [sboyd@codeaurora.org: Massaged to work with devm friendly qcom_cc_probe()] Signed-off-by: Stephen Boyd

clk: qcom: Move gdsc config outside COMMON_CLK_QCOM config

2015-10-09T06:53:02+00:00

Having this hidden config below the COMMON_CLK_QCOM config causes menuconfig to stop indenting config items after it. <*> Support for Qualcomm's clock controllers {M} APQ8084 Global Clock Controller APQ8084 Multimedia Clock Controller {M} IPQ806x Global Clock Controller IPQ806x LPASS Clock Controller MSM8660 Global Clock Controller MSM8916 Global Clock Controller {M} APQ8064/MSM8960 Global Clock Controller APQ8064/MSM8960 LPASS Clock Controller MSM8960 Multimedia Clock Controller {M} MSM8974 Global Clock Controller MSM8974 Multimedia Clock Controller Move it up above anything else so that we don't get odd indenting. Cc: Rajendra Nayak Signed-off-by: Stephen Boyd

clk: qcom: Drop calls to qcom_cc_remove()

2015-10-09T06:53:01+00:00

Now that qcom_cc_remove() is a nop, drop calls to qcom_cc_remove() and any empty driver remove functions. Cc: Rajendra Nayak Signed-off-by: Stephen Boyd