kernel/linux.git/drivers/clk/qcom, branch v4.11.5

clk: qcom: Do not drop device node twice

2017-02-16T01:17:55+00:00

of_find_node_by_name() drops the reference to a passed device node. It is not necessary to drop it again, and doing so may result in the device node being released prematurely. Cc: Rob Herring Signed-off-by: Guenter Roeck Fixes: ee15faffef11 ("clk: qcom: common: Add API to register board clocks backwards compatibly") Signed-off-by: Stephen Boyd

clk: qcom: SDHCI enablement on Nexus 5X / 6P

2017-01-27T21:33:05+00:00

Add missing clock branch to enable onboard storage for msm899(2/4). Signed-off-by: Jeremy McNicoll Signed-off-by: Stephen Boyd

clk: qcom: gdsc: Fix handling of hw control enable/disable

2017-01-27T00:00:38+00:00

Once a gdsc is brought in and out of HW control, there is a power down and up cycle which can take upto 1us. Polling on the gdsc status immediately after the hw control enable/disable can mislead software/firmware to belive the gdsc is already either on or off, while its yet to complete the power cycle. To avoid this add a 1us delay post a enable/disable of HW control mode. Also after the HW control mode is disabled, poll on the status to check gdsc status reflects its 'on' before force disabling it in software. Reported-by: Stanimir Varbanov Reviewed-by: Stanimir Varbanov Tested-by: Stanimir Varbanov Signed-off-by: Rajendra Nayak Fixes: 904bb4f5c7de ("clk: qcom: gdsc: Add support for gdscs with HW control") Signed-off-by: Stephen Boyd

clk: mdm9615: Add EBI2 clock

2017-01-10T00:33:26+00:00

Add definition of EBI2 clock used by MDM9615 NAND controller. Cc: Andy Gross Cc: David Brown Cc: Michael Turquette Cc: Stephen Boyd Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-msm@vger.kernel.org Cc: linux-soc@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Zoran Markovic Acked-by: Neil Armstrong [sboyd@codeaurora.org: ebi2_clk halt bit is 24 not 23] Signed-off-by: Stephen Boyd

clk: qcom: Add GCC_MSS_RESET support

2017-01-10T00:06:43+00:00

Add support to use reset control framework for resetting MSS with hexagon v56 1.5.0. Signed-off-by: Avaneesh Kumar Dwivedi Reviewed-by: Bjorn Andersson Signed-off-by: Stephen Boyd

Merge branches 'clk-qcom-rpm8974', 'clk-stm32f4', 'clk-ipq4019' and 'clk-fixes' into clk-next

2017-01-10T00:06:11+00:00

* clk-qcom-rpm8974: clk: qcom: smd-rpmcc: Add msm8974 clocks * clk-stm32f4: clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board clk: stm32f4: Add SAI clocks clk: stm32f4: Add I2S clock clk: stm32f4: Add lcd-tft clock clk: stm32f4: Add post divisor for I2S & SAI PLLs clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards clk: stm32f4: Update DT bindings documentation * clk-ipq4019: clk: qcom: ipq4019: Add the cpu clock frequency change notifier clk: qcom: ipq4019: Add all the frequencies for apss cpu clk: qcom: ipq4019: correct sdcc frequency and parent name clk: qcom: ipq4019: Add the nodes for pcnoc clk: qcom: ipq4019: Add the apss cpu pll divider clock node clk: qcom: ipq4019: remove fixed clocks and add pll clocks * clk-fixes: clk: stm32f4: Use CLK_OF_DECLARE_DRIVER initialization method clk: renesas: mstp: Support 8-bit registers for r7s72100

clk: qcom: ipq4019: Add the cpu clock frequency change notifier

2016-12-27T21:44:34+00:00

The current driver code gives the crash or gets hang while switching the CPU frequency some time. The APSS CPU Clock divider is not glitch free so it the APPS clock need to be switched for stable clock during the change. This patch adds the frequency change notifier for APSS CPU clock. It changes the parent of this clock to stable PLL FEPLL500 for PRE_RATE_CHANGE event. This event will be generated before actual clock set operations. The clock set operation will again change its corresponding parent by getting the same from frequency table. Signed-off-by: Abhishek Sahu [sboyd@codeaurora.org: Indent less in probe] Signed-off-by: Stephen Boyd

clk: qcom: smd-rpmcc: Add msm8974 clocks

2016-12-22T00:04:35+00:00

This adds all RPM based clocks for msm8974, except cxo and gfx3d_clk_src. Tested-by: Georgi Djakov Signed-off-by: Bjorn Andersson Acked-by: Rob Herring Signed-off-by: Stephen Boyd

clk: qcom: ipq4019: Add all the frequencies for apss cpu

2016-12-21T23:57:29+00:00

The APSS CPU clock does not contain all the frequencies in its frequency table so this patch adds the same. Signed-off-by: Abhishek Sahu Signed-off-by: Stephen Boyd

clk: qcom: ipq4019: correct sdcc frequency and parent name

2016-12-21T23:57:28+00:00

1. The parent for sdcc clock is sdccpll. 2. The frequency value was wrong so modified the same. Signed-off-by: Abhishek Sahu Signed-off-by: Stephen Boyd