<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/clk/qcom, branch v3.18.62</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v3.18.62</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v3.18.62'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2016-07-12T12:48:02+00:00</updated>
<entry>
<title>clk: qcom: msm8960: Fix ce3_src register offset</title>
<updated>2016-07-12T12:48:02+00:00</updated>
<author>
<name>Stephen Boyd</name>
<email>sboyd@codeaurora.org</email>
</author>
<published>2016-03-02T01:26:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d9d898db8e45b25a3293c98317fbcdc2ed5f8adc'/>
<id>urn:sha1:d9d898db8e45b25a3293c98317fbcdc2ed5f8adc</id>
<content type='text'>
[ Upstream commit 0f75e1a370fd843c9e508fc1ccf0662833034827 ]

The offset seems to have been copied from the sata clk. Fix it so
that enabling the crypto engine source clk works.

Tested-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Tested-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Sasha Levin &lt;sasha.levin@oracle.com&gt;
</content>
</entry>
<entry>
<title>clk: qcom: msm8960: fix ce3_core clk enable register</title>
<updated>2016-07-12T12:48:01+00:00</updated>
<author>
<name>Srinivas Kandagatla</name>
<email>srinivas.kandagatla@linaro.org</email>
</author>
<published>2016-02-22T11:43:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=66e0e452e09345e95d7fa781d6d3c0c36c47b438'/>
<id>urn:sha1:66e0e452e09345e95d7fa781d6d3c0c36c47b438</id>
<content type='text'>
[ Upstream commit 732d6913691848db9fabaa6a25b4d6fad10ddccf ]

This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4

Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Sasha Levin &lt;sasha.levin@oracle.com&gt;
</content>
</entry>
<entry>
<title>clk: qcom: fix RCG M/N counter configuration</title>
<updated>2015-05-17T23:12:19+00:00</updated>
<author>
<name>Archit Taneja</name>
<email>architt@codeaurora.org</email>
</author>
<published>2015-03-04T09:49:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=5ec6388f8e752c6f63caf859ad2be687668c3389'/>
<id>urn:sha1:5ec6388f8e752c6f63caf859ad2be687668c3389</id>
<content type='text'>
[ Upstream commit 0b21503dbbfa669dbd847b33578d4041513cddb2 ]

Currently, a RCG's M/N counter (used for fraction division) is
set to either 'bypass' (counter disabled) or 'dual edge' (counter
enabled) based on whether the corresponding rcg struct has a mnd
field specified and a non-zero N.

In the case where M and N are the same value, the M/N counter is
still enabled by code even though no division takes place.
Leaving the RCG in such a state can result in improper behavior.
This was observed with the DSI pixel clock RCG when M and N were
both set to 1.

Add an additional check (M != N) to enable the M/N counter only
when it's needed for fraction division.

Signed-off-by: Archit Taneja &lt;architt@codeaurora.org&gt;
Fixes: bcd61c0f535a (clk: qcom: Add support for root clock
generators (RCGs))
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;

Signed-off-by: Sasha Levin &lt;sasha.levin@oracle.com&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Fix i2c frequency table</title>
<updated>2015-05-17T23:12:19+00:00</updated>
<author>
<name>Stephen Boyd</name>
<email>sboyd@codeaurora.org</email>
</author>
<published>2015-02-23T21:30:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d415fc1d430b6f0a5c1011bf9830fcdb756a8718'/>
<id>urn:sha1:d415fc1d430b6f0a5c1011bf9830fcdb756a8718</id>
<content type='text'>
[ Upstream commit 0bf0ff82c34da02ee5795101b328225a2d519594 ]

PXO is 25MHz, not 27MHz. Fix the table.

Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global
clock controller (GCC)"

Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Reviewed-by: Andy Gross &lt;agross@codeaurora.org&gt;
Tested-by: Andy Gross &lt;agross@codeaurora.org&gt;
Signed-off-by: Michael Turquette &lt;mturquette@linaro.org&gt;
Signed-off-by: Sasha Levin &lt;sasha.levin@oracle.com&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Fix duplicate rbcpr clock name</title>
<updated>2014-11-17T18:40:42+00:00</updated>
<author>
<name>Georgi Djakov</name>
<email>gdjakov@mm-sol.com</email>
</author>
<published>2014-10-10T13:57:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9a6cb70f40b0268297024949eb0a2689e3b7769b'/>
<id>urn:sha1:9a6cb70f40b0268297024949eb0a2689e3b7769b</id>
<content type='text'>
There is a duplication in a clock name for apq8084 platform that causes
the following warning: "RBCPR_CLK_SRC" redefined

Resolve this by adding a MMSS_ prefix to this clock and making its name
coherent with msm8974 platform.

Fixes: 2b46cd23a5a2 ("clk: qcom: Add APQ8084 Multimedia Clock Controller (MMCC) support")
Signed-off-by: Georgi Djakov &lt;gdjakov@mm-sol.com&gt;
Reviewed-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Michael Turquette &lt;mturquette@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'qcom-clocks-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into clk-next</title>
<updated>2014-09-26T23:10:57+00:00</updated>
<author>
<name>Mike Turquette</name>
<email>mturquette@linaro.org</email>
</author>
<published>2014-09-26T23:10:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=db0bcc33a8aabab462c996baeac619f21616d938'/>
<id>urn:sha1:db0bcc33a8aabab462c996baeac619f21616d938</id>
<content type='text'>
qcom clock changes for 3.18

Some fixes for the IPQ driver and some code consolidation
and refactoring.
</content>
</entry>
<entry>
<title>clk: Remove .owner field for driver</title>
<updated>2014-09-26T00:43:31+00:00</updated>
<author>
<name>Kiran Padwal</name>
<email>kiran.padwal@smartplayin.com</email>
</author>
<published>2014-09-24T09:45:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=59c0621d4d5fa4faeb8a0cdd0cfe27c13fdd09b2'/>
<id>urn:sha1:59c0621d4d5fa4faeb8a0cdd0cfe27c13fdd09b2</id>
<content type='text'>
There is no need to init .owner field.

Based on the patch from Peter Griffin &lt;peter.griffin@linaro.org&gt;
"mmc: remove .owner field for drivers using module_platform_driver"

This patch removes the superflous .owner field for drivers which
use the module_platform_driver API, as this is overriden in
platform_driver_register anyway."

Signed-off-by: Kiran Padwal &lt;kiran.padwal@smartplayin.com&gt;
Signed-off-by: Mike Turquette &lt;mturquette@linaro.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Add support for banked MD RCGs</title>
<updated>2014-09-22T22:16:54+00:00</updated>
<author>
<name>Stephen Boyd</name>
<email>sboyd@codeaurora.org</email>
</author>
<published>2014-04-28T22:59:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=229fd4a505553c3a475b90e9aa8e452f5d78eb3b'/>
<id>urn:sha1:229fd4a505553c3a475b90e9aa8e452f5d78eb3b</id>
<content type='text'>
The banked MD RCGs in global clock control have a different
register layout than the ones implemented in multimedia clock
control. Add support for these types of clocks so we can change
the rates of the UBI32 clocks.

Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Add support for setting rates on PLLs</title>
<updated>2014-09-22T22:16:53+00:00</updated>
<author>
<name>Stephen Boyd</name>
<email>sboyd@codeaurora.org</email>
</author>
<published>2014-04-28T22:58:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ae3669ac5c09fa8dfc8d8a294ccb5f265b8929be'/>
<id>urn:sha1:ae3669ac5c09fa8dfc8d8a294ccb5f265b8929be</id>
<content type='text'>
Some PLLs may require changing their rate at runtime. Add support
for these PLLs.

Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Consolidate frequency finding logic</title>
<updated>2014-09-22T22:16:52+00:00</updated>
<author>
<name>Stephen Boyd</name>
<email>sboyd@codeaurora.org</email>
</author>
<published>2014-09-04T20:21:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=50c6a50344c58f73c697e2fe38960dc176a2e69f'/>
<id>urn:sha1:50c6a50344c58f73c697e2fe38960dc176a2e69f</id>
<content type='text'>
There are two find_freq() functions in clk-rcg.c and clk-rcg2.c
that are almost exactly the same. Consolidate them into one
function to save on some code space.

Cc: Mike Turquette &lt;mturquette@linaro.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
</feed>
