kernel/linux.git/drivers/clk/qcom/hfpll.c, branch v6.12.80

clk: qcom: hfpll: Add QCS404-specific compatible

2024-04-23T19:14:47+00:00

It doesn't appear that the configuration is for the HFPLL is generic, so add a qcs404-specific compatible and rename the existing struct to qcs404. Keep qcom,hfpll in the driver for compatibility with old dtbs. Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20240218-hfpll-yaml-v2-2-31543e0d6261@z3ntu.xyz Signed-off-by: Bjorn Andersson

clk: qcom: hfpll: Add MSM8976 PLL data

2023-09-13T19:07:59+00:00

Add PLL configuration for MSM8976 SoC, this SoC offers 3 HFPLL. Small cluster offers two presets for 652-902Mhz range and 902Mhz-1.47Ghz. For simplicity only add second range as smaller frequencies can be obtained via apcs divider or safe parent this also saves us a hassle of reconfiguring VCO bit and config_val. A72 and CCI cluster only use single frequency range with their outputs/post_dividers/vco_bits being static. Signed-off-by: Adam Skladowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230812112534.8610-6-a39.skl@gmail.com Signed-off-by: Bjorn Andersson

clk: qcom: hfpll: Allow matching pdata

2023-09-13T19:07:59+00:00

HFPLL driver can be used to drive PLLs also on different SoCs like MSM8976 On MSM8976 each PLL gets it own different configuration, add matching pdata to driver to support multiple configurations. Signed-off-by: Adam Skladowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230812112534.8610-4-a39.skl@gmail.com Signed-off-by: Bjorn Andersson

clk: qcom: hfpll: use devm_platform_get_and_ioremap_resource()

2022-12-01T23:26:40+00:00

Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Minghao Chi Signed-off-by: ye xingchen Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/202211171403340042731@zte.com.cn

clk: qcom: hfpll: use clk_parent_data to specify the parent

2019-12-19T06:07:52+00:00

This permits extending the driver to other platforms without having to modify its source code. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Link: https://lkml.kernel.org/r/20191125135910.679310-6-niklas.cassel@linaro.org Signed-off-by: Stephen Boyd

clk: qcom: hfpll: CLK_IGNORE_UNUSED

2019-12-19T06:07:52+00:00

When COMMON_CLK_DISABLED_UNUSED is set, in an effort to save power and to keep the software model of the clock in line with reality, the framework transverses the clock tree and disables those clocks that were enabled by the firmware but have not been enabled by any device driver. If CPUFREQ is enabled, early during the system boot, it might attempt to change the CPU frequency ("set_rate"). If the HFPLL is selected as a provider, it will then change the rate for this clock. As boot continues, clk_disable_unused_subtree will run. Since it wont find a valid counter (enable_count) for a clock that is actually enabled it will attempt to disable it which will cause the CPU to stop. Notice that in this driver, calls to check whether the clock is enabled are routed via the is_enabled callback which queries the hardware. The following commit, rather than marking the clock critical and forcing the clock to be always enabled, addresses the above scenario making sure the clock is not disabled but it continues to rely on the firmware to enable the clock. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson Link: https://lkml.kernel.org/r/20191125135910.679310-5-niklas.cassel@linaro.org Signed-off-by: Stephen Boyd

clk: qcom: hfpll: register as clock provider

2019-12-19T06:07:52+00:00

Make the output of the high frequency pll a clock provider. On the QCS404 this PLL controls cpu frequency scaling. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson Acked-by: Stephen Boyd Link: https://lkml.kernel.org/r/20191125135910.679310-4-niklas.cassel@linaro.org Signed-off-by: Stephen Boyd

clk: qcom: Add HFPLL driver

2018-10-17T20:14:40+00:00

On some devices (MSM8974 for example), the HFPLLs are instantiated within the Krait processor subsystem as separate register regions. Add a driver for these PLLs so that we can provide HFPLL clocks for use by the system. Cc: Signed-off-by: Stephen Boyd Signed-off-by: Sricharan R Tested-by: Craig Tatlor Signed-off-by: Stephen Boyd